component
SCT2630ASTER
Public Made by Adomby adom
SCT DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
cc9c05d
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{
"schema": "adom.pads/1",
"slug": "sct2630aster",
"footprint": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm",
"generated_from": {
"footprint": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm@sha256:5848244c5e72002e",
"pins": "page.json:component.pins",
"overrides": null
},
"pin1": {
"pad": "1",
"at": [
-2.475,
-1.905
],
"corner": "top-left",
"source": "silk-marker",
"derived_from": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm@sha256:5848244c5e72002e"
},
"pad_count": 9,
"symbol_pins": [
"1",
"2",
"3",
"4",
"5",
"6",
"7",
"8",
"9"
],
"paste_apertures": 4,
"issues": [],
"pads": [
{
"pad": "1",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
-1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "1",
"name": "BOOT",
"type": "power_in",
"description": "Power supply bias for high-side power MOSFET gate driver. Connect a 0.1µF bootstrap capacitor from BOOT to SW. Bootstrap capacitor is charged when SW is low. Absolute max 72V; BOOT-SW rated -0.3 to 6V, UVLO threshold ~2.52V.",
"is_pin1": true,
"source": {
"geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "2",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
-0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "2",
"name": "VIN",
"type": "power_in",
"description": "Input supply voltage, 4.5V to 60V operating range (absolute max 65V). Connect a local high-frequency bypass capacitor from VIN to GND as close as possible to the pin.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "3",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "3",
"name": "EN",
"type": "input",
"description": "Enable input with internal 1µA pull-up current source (3.6µA once above threshold). Pull below 1.2V to disable the converter; float or tie to VIN to enable. A VIN-to-GND resistor divider on EN sets a programmable input UVLO threshold. High-voltage tolerant to 65V.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "4",
"kind": "smd",
"shape": "roundrect",
"at": [
-2.475,
1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "4",
"name": "RT/CLK",
"type": "bidirectional",
"description": "Sets internal oscillator frequency or accepts an external synchronization clock. A resistor from RT/CLK to GND sets fSW from 100kHz to 1.2MHz (RT(kΩ) = 100000/fSW(kHz), typical pin voltage 0.5V). Alternatively, drive an external clock (100kHz-1.2MHz, high ≥2V, low ≤0.4V, pulse width >80ns) directly into RT/CLK; internal PLL locks to it. On loss of clock, reverts to resistor-set frequency.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "5",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "5",
"name": "FB",
"type": "input",
"description": "Inverting input of the transconductance error amplifier. Connect the tap of an external feedback resistor divider from VOUT to GND. Device regulates FB to the internal 0.8V ±1% reference. OVP triggers at 110% of VREF (rising), releases at 105% (falling).",
"is_pin1": false,
"source": {
"geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "6",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "6",
"name": "COMP",
"type": "output",
"description": "Error amplifier output. Connect an external frequency compensation network (R-C) to GND to shape the control loop. Typical clamps: high 2.25V, low 0.47V. Transconductance gm ≈ 300µS, ±30µA source/sink.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "7",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
-0.635
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "7",
"name": "GND",
"type": "power_in",
"description": "Ground return for the device. Electrically connected to the exposed thermal pad.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "8",
"kind": "smd",
"shape": "roundrect",
"at": [
2.475,
-1.905
],
"rot": 0.0,
"size": [
1.95,
0.6
],
"layers": [
"F.Cu",
"F.Mask",
"F.Paste"
],
"thermal": false,
"pin": "8",
"name": "SW",
"type": "output",
"description": "Regulator switching output - source of the integrated 80mΩ high-side MOSFET. Connect to the external power inductor and to the external low-side (catch) Schottky diode. Absolute max -1V to 65V. Also serves as the BOOT capacitor return.",
"is_pin1": false,
"source": {
"geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
},
{
"pad": "9",
"kind": "smd",
"shape": "rect",
"at": [
0.0,
0.0
],
"rot": 0.0,
"size": [
2.41,
3.3
],
"layers": [],
"thermal": true,
"pin": "9",
"name": "Thermal Pad",
"type": "passive",
"description": "Exposed thermal pad on the underside of the ESOP-8 package. Heat-dissipation path of the die; electrically connected to the GND pin. Must be soldered to a ground copper plane on the PCB for proper operation and optimized thermal performance (θJA ≈ 42°C/W).",
"is_pin1": false,
"source": {
"geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm.kicad_mod",
"meaning": "page.json:component.pins",
"correspondence": "kicad: symbol pin number == pad name"
}
}
]
}