component
SCT2450QSTER
Public Made by Adomby adom
SCT DC-DC Converters, ESOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSCT2450QSTER
SCT · DC-DC Converters · ESOP-8
SCT2450QSTER from SCT, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Power supply bias for the high-side power MOSFET gate driver. Connect a 0.1 µF bootstrap capacitor from BOOT to SW. The bootstrap capacitor is charged when the low-side MOSFET is on or SW is low. Absolute max 44 V (BOOT-SW max 6 V). |
| 2 | VIN | power_in | Input supply voltage, 3.8 V to 36 V operating (absolute max 38 V, 42 V transient 300 ms). Connect a local high-frequency bypass capacitor from VIN to GND as short as possible. |
| 3 | EN | input | Enable pin to the regulator with internal pull-up current source (1.5 µA typ at 1 V). Pull below 1.1 V to disable the converter; float or tie to VIN to enable. A resistor divider from VIN to GND to EN can program the input UVLO threshold. Enable high threshold 1.18 V typ. |
| 4 | RT/CLK | bidirectional | Frequency set / external clock input. Connect a resistor from RT/CLK to GND to set the internal oscillator frequency (100 kHz to 2.2 MHz). Alternatively drive with an external clock (100 kHz-2.2 MHz); the internal PLL synchronizes to the external clock and reverts to resistor-set frequency if clock edges stop. |
| 5 | FB | input | Inverting input of the trans-conductance error amplifier. Tap an external resistor divider from VOUT to GND to set the output voltage; the device regulates FB to the internal reference of 0.8 V (±1%) typical. |
| 6 | COMP | output | Error amplifier output. Connect a frequency loop compensation network (typically series R + C, optional parallel C) from COMP to GND. Clamp voltages: high 3 V, low 0.4 V. |
| 7 | GND | power_in | Device ground return. |
| 8 | SW | power_out | Regulator switching node. Connect SW to the external power inductor. This is the switch node between the integrated high-side (48 mΩ) and low-side (23 mΩ) power MOSFETs. Absolute max range -1 V to 38 V. |
| 9 | Thermal Pad | power_in | Exposed thermal pad on the ESOP-8 package. Heat dissipation path of the die; electrically connected to GND. Must be soldered to the PCB ground plane for proper operation and optimized thermal performance (θJA ≈ 42 °C/W, θJC ≈ 45.8 °C/W). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SCT |
| Package | ESOP-8 |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
SCT2450QSTER
CAD (KiCad official)
- Symbol:
SCT2450QSTER - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
sct2450qster-etched.step/sct2450qster-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sct2450qster.step/sct2450qster.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SCT datasheet (22 pp, sha256
74bb039979bfaa07, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).