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Contents

README

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SCT2432STER

SCT · DC-DC Converters · ESOP-8

SCT2432STER from SCT, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOOT passive Power supply bias for the high-side power MOSFET gate driver. Connect a 0.1µF bootstrap capacitor from BOOT to SW. Capacitor is charged when the low-side power MOSFET is on or SW voltage is low. Absolute max 46V; BOOT-SW max 6V; BOOT-SW UVLO threshold ~2.36V.
2 VIN power_in Input supply voltage, 3.8V to 40V operating range (absolute max 42V). Connect a local bypass capacitor from VIN to GND with the shortest possible path from VIN to the high-frequency bypass capacitor and GND.
3 EN input Enable pin to the regulator with internal pull-up current source (1.5µA at 1V, 5.5µA at 1.5V). Pull below 1.1V to disable the converter; float or connect to VIN to enable. Enable rising threshold ~1.18V. Tap of a VIN-to-GND resistor divider on EN can set the input UVLO threshold. Absolute max 42V.
4 RT/CLK bidirectional Sets internal oscillator switching frequency or accepts an external synchronization clock. Connect a resistor from this pin to GND to program frequency between 300kHz and 2.2MHz (RT[kΩ] = 100000 / fsw[kHz]); or drive with an external clock (high >2V, low <0.4V, pulse >80ns) and the internal PLL will lock. Must not be left floating or shorted to GND. Absolute max 6V.
5 FB input Inverting input of the trans-conductance error amplifier. Connect to the tap of the output-to-GND feedback resistor divider that programs the output voltage. Device regulates FB to the internal 0.8V (±1%) reference. Overvoltage protection trips at ~110% of VREF. Absolute max 6V.
6 SS passive Soft-start programming pin. Connect a ceramic capacitor from SS to GND to set soft-start time; an internal 3µA current source pulls SS toward VCC. Css = tss * 3µA / 0.8V; programmed soft-start time should be greater than 4ms. Absolute max 6V.
7 GND power_in Device ground. Must be tied to the PCB ground plane together with the exposed thermal pad.
8 SW power_out Regulator switching node; source of the internal high-side MOSFET and drain of the low-side MOSFET. Connect to an external power inductor to feed the LC output filter. Absolute max 42V.
9 Thermal Pad power_in Exposed thermal pad on the die back - heat dissipation path. Must be electrically connected to the GND pin and soldered to the PCB ground plane for proper operation and optimized thermal performance (RθJA ≈ 42°C/W).

Key specifications

Parameter Value
Manufacturer SCT
Package ESOP-8
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • SCT2432STER

CAD (KiCad official)

  • Symbol: SCT2432STER
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: ESOP-8 (KiCad packages3D, STEP)
  • 3D model files: sct2432ster-etched.step / sct2432ster-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sct2432ster.step / sct2432ster.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sct2432ster.step 125 KB You want the bare part, or you mark your own boards.
sct2432ster-etched.step 2.4 MB You want the part with SCT2432STER already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 591 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SCT datasheet (22 pp, sha256 cdce43b0bc463e30, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF