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SCAN90CP02VY

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Texas Instruments Signal Switches, Multiplexers, Decoders, LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SCAN90CP02VY

Texas Instruments · Signal Switches, Multiplexers, Decoders · LQFP-32(7x7)

SCAN90CP02VY from Texas Instruments, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PEM11 input Channel 1 output pre-emphasis control input (LVTTL), which together with PEM10 selects 0/25/50/100% pre-emphasis per Table 1.
2 PEM10 input Channel 1 output pre-emphasis control input (LVTTL), which together with PEM11 selects 0/25/50/100% pre-emphasis per Table 1.
3 PEM01 input Channel 0 output pre-emphasis control input (LVTTL), which together with PEM00 selects 0/25/50/100% pre-emphasis per Table 1.
4 PEM00 input Channel 0 output pre-emphasis control input (LVTTL), which together with PEM01 selects 0/25/50/100% pre-emphasis per Table 1.
5 GND power_in Ground reference to LVDS and CMOS circuitry.
6 SEL1 input Configuration select control input (LVTTL) that, with SEL0, EN0 and EN1, sets the crosspoint mode per the configuration select truth table.
7 SEL0 input Configuration select control input (LVTTL) that, with SEL1, EN0 and EN1, sets the crosspoint mode per the configuration select truth table.
8 EN0 input Channel 0 output enable input (LVTTL); together with EN1 and the SEL inputs it selects the mode per the truth table.
9 IN0+ input Non-inverting differential input, LVDS, Bus LVDS, CML or LVPECL compatible, with VCMR of 0.05 V to 3.55 V and VID of at least 100 mV.
10 IN0- input Inverting differential input, LVDS, Bus LVDS, CML or LVPECL compatible, with VCMR of 0.05 V to 3.55 V and VID of at least 100 mV.
11 GND power_in Ground reference to LVDS and CMOS circuitry.
12 VDDA power_in Supply pin, VDD = 3.3 V ±0.3 V (3.0 V to 3.6 V); at least 4 low-ESR 0.01 µF bypass capacitors should be connected from VDD to the GND plane.
13 IN1+ input Non-inverting differential input, LVDS, Bus LVDS, CML or LVPECL compatible, with VCMR of 0.05 V to 3.55 V and VID of at least 100 mV.
14 IN1- input Inverting differential input, LVDS, Bus LVDS, CML or LVPECL compatible, with VCMR of 0.05 V to 3.55 V and VID of at least 100 mV.
15 GND power_in Ground reference to LVDS and CMOS circuitry.
16 VDD2 power_in Supply pin, VDD = 3.3 V ±0.3 V (3.0 V to 3.6 V); at least 4 low-ESR 0.01 µF bypass capacitors should be connected from VDD to the GND plane.
17 EN1 input Channel 1 output enable input (LVTTL); together with EN0 and the SEL inputs it selects the mode per the truth table.
18 VDD1 power_in Supply pin, VDD = 3.3 V ±0.3 V (3.0 V to 3.6 V); at least 4 low-ESR 0.01 µF bypass capacitors should be connected from VDD to the GND plane.
19 TCK input Test clock input for IEEE 1149.1 (JTAG) support, LVTTL; maximum TCK clock frequency is 25.0 MHz.
20 GND power_in Ground reference to LVDS and CMOS circuitry.
21 TMS input Test mode select input for IEEE 1149.1 (JTAG) support, LVTTL.
22 TDI input Test data input for IEEE 1149.1 (JTAG) support, LVTTL; internal pull-down with IILR of -40 µA to -200 µA.
23 TDO output Test data output for IEEE 1149.1 (JTAG) support, LVTTL; VOH at least 2.4 V at IOH = -12 mA and VOL at most 0.5 V at IOL = 12 mA at VDD = 3.0 V.
24 TRST input Test reset input for IEEE 1149.1 (JTAG) support, LVTTL; minimum pulse width 2.5 ns (active low).
25 VDD2 power_in Supply pin, VDD = 3.3 V ±0.3 V (3.0 V to 3.6 V); at least 4 low-ESR 0.01 µF bypass capacitors should be connected from VDD to the GND plane.
26 GND power_in Ground reference to LVDS and CMOS circuitry.
27 OUT1- output Inverting switched LVDS differential output that can be connected to any one pair IN0± or IN1±; point-to-point use only, not multidrop BLVDS.
28 OUT1+ output Non-inverting switched LVDS differential output that can be connected to any one pair IN0± or IN1±; point-to-point use only, not multidrop BLVDS.
29 VDDA power_in Supply pin, VDD = 3.3 V ±0.3 V (3.0 V to 3.6 V); at least 4 low-ESR 0.01 µF bypass capacitors should be connected from VDD to the GND plane.
30 GND power_in Ground reference to LVDS and CMOS circuitry.
31 OUT0- output Inverting switched LVDS differential output that can be connected to any one pair IN0± or IN1±; point-to-point use only, not multidrop BLVDS.
32 OUT0+ output Non-inverting switched LVDS differential output that can be connected to any one pair IN0± or IN1±; point-to-point use only, not multidrop BLVDS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-32(7x7)
Category Logic
Pins 32

CAD (KiCad official)

  • Symbol: SCAN90CP02VY
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: scan90cp02vy-etched.step / scan90cp02vy-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); scan90cp02vy.step / scan90cp02vy.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 406fd9fb645aee09, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF