component
SA24403FCA
Public Made by Adomby adom
Silergy Corp DC-DC Converters, ESOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SA24403FCA
Silergy Corp · DC-DC Converters · ESOP-8
SA24403FCA from Silergy Corp, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BS | passive | Boot-strap pin that supplies the high-side gate driver; connect a 0.1µF ceramic capacitor between BS and LX. |
| 2 | LX | output | Inductor pin connected to the switching node; absolute maximum rating is -0.3V to 44V to GND. |
| 3 | IN | power_in | Input supply pin, operating range 4.2V to 40V, to be decoupled to GND with at least a 4.7µF ceramic capacitor. |
| 4 | EN | input | Enable control that turns the regulator on when pulled high and must not be left floating. |
| 5 | FB | input | Output feedback pin connected to the center point of the output resistor divider, programming VOUT = 0.6×(1+R1/R2). |
| 6 | FS | input | Frequency setting pin; a resistor from FS to GND sets the switching frequency per fsw(kHz)=10^6/(9.3×RFS(kΩ)+30), adjustable from 300kHz to 2.2MHz. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | PG | output | Open-drain power-good output that is externally pulled high when VOUT is within regulation range and internally pulled low otherwise. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | ESOP-8 |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.2 | 40 | V | 4 | ||
| Input UVLO Threshold | VUVLO | 3.6 | 3.9 | 4.2 | V | 4 | |
| Quiescent Current | IQ | 10 | 18 | 25 | µA | IOUT=0, VFB=VREF×105%, TJ=25°C | 4 |
| Quiescent Current | IQ | 5 | 18 | 33 | µA | IOUT=0, VFB=VREF×105%, TJ= -40°C~125°C | 4 |
| FB Input Current | IFB | -50 | 50 | nA | VFB=0.65V | 4 | |
| Feedback Reference Voltage | VREF | 0.594 | 0.6 | 0.606 | V | TJ= 25°C | 4 |
| Feedback Reference Voltage | VREF | 0.588 | 0.6 | 0.612 | V | TJ= -40°C~125°C | 4 |
| Top FET RON | RDS(ON)1 | 70 | 115 | 210 | mΩ | 4 | |
| Bottom FET RON | RDS(ON)2 | 45 | 80 | 135 | mΩ | 4 | |
| Top FET Current Limit | ILIM,TOP | 4.4 | 5.5 | 6.6 | A | 4 | |
| EN High Threshold | VENH | 1.08 | 1.2 | 1.32 | V | 4 | |
| EN Low Threshold | VENL | 0.9 | 1 | 1.1 | V | 4 | |
| Oscillator Frequency Program Range | fOSC,RNG | 300 | 2200 | kHz | RFS=45.6k~360k | 4 | |
| Oscillator Frequency Accuracy | fOSC,ACC | -12 | 12 | % | fOSC=2MHz, with RFS resistor of 1% accuracy | 4 | |
| Soft-start Time | tSS | 0.5 | 1 | 2 | ms | 4 | |
| Input Voltage (Absolute Maximum), IN to GND | -0.3 | 44 | V | 3 | |||
| Voltage on LX, FB, EN, FS, PG to GND | -0.3 | 44 | V | 3 | |||
| BS-LX Voltage | 4 | V | 3 | ||||
| Power Dissipation | PD | 2.5 | W | TA = 25°C, SO8E | 3 | ||
| Junction Temperature Range | -40 | 150 | °C | 3 | |||
| Lead Temperature (Soldering) | 260 | °C | 10 sec soldering | 3 | |||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Supply Input Voltage | 4.2 | 40 | V | 3 | |||
| Ambient Temperature Range | -40 | 125 | °C | 3 | |||
| Package Thermal Resistance, junction-to-ambient | θJA | 40 | °C/W | Note 2: measured in natural convection at TA=25°C, two-layer Silergy demo board | 3 | ||
| Package Thermal Resistance, junction-to-case | θJC | 12 | °C/W | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | 3) The PCB copper area associated with the LX pin | 9 |
CAD (KiCad official)
- Symbol:
SA24403FCA - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm - 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files:
sa24403fca-etched.step/sa24403fca-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sa24403fca.step/sa24403fca.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silergy Corp datasheet (13 pp, sha256
8ba79a1eb4c8bf1c, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SA24403FCA
**Silergy Corp** · DC-DC Converters · ESOP-8
SA24403FCA from Silergy Corp, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BS | passive | Boot-strap pin that supplies the high-side gate driver; connect a 0.1µF ceramic capacitor between BS and LX. |
| 2 | LX | output | Inductor pin connected to the switching node; absolute maximum rating is -0.3V to 44V to GND. |
| 3 | IN | power_in | Input supply pin, operating range 4.2V to 40V, to be decoupled to GND with at least a 4.7µF ceramic capacitor. |
| 4 | EN | input | Enable control that turns the regulator on when pulled high and must not be left floating. |
| 5 | FB | input | Output feedback pin connected to the center point of the output resistor divider, programming VOUT = 0.6×(1+R1/R2). |
| 6 | FS | input | Frequency setting pin; a resistor from FS to GND sets the switching frequency per fsw(kHz)=10^6/(9.3×RFS(kΩ)+30), adjustable from 300kHz to 2.2MHz. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | PG | output | Open-drain power-good output that is externally pulled high when VOUT is within regulation range and internally pulled low otherwise. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silergy Corp |
| Package | ESOP-8 |
| Category | Power Management (PMIC) |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range | VIN | 4.2 | | 40 | V | | 4 |
| Input UVLO Threshold | VUVLO | 3.6 | 3.9 | 4.2 | V | | 4 |
| Quiescent Current | IQ | 10 | 18 | 25 | µA | IOUT=0, VFB=VREF×105%, TJ=25°C | 4 |
| Quiescent Current | IQ | 5 | 18 | 33 | µA | IOUT=0, VFB=VREF×105%, TJ= -40°C~125°C | 4 |
| FB Input Current | IFB | -50 | | 50 | nA | VFB=0.65V | 4 |
| Feedback Reference Voltage | VREF | 0.594 | 0.6 | 0.606 | V | TJ= 25°C | 4 |
| Feedback Reference Voltage | VREF | 0.588 | 0.6 | 0.612 | V | TJ= -40°C~125°C | 4 |
| Top FET RON | RDS(ON)1 | 70 | 115 | 210 | mΩ | | 4 |
| Bottom FET RON | RDS(ON)2 | 45 | 80 | 135 | mΩ | | 4 |
| Top FET Current Limit | ILIM,TOP | 4.4 | 5.5 | 6.6 | A | | 4 |
| EN High Threshold | VENH | 1.08 | 1.2 | 1.32 | V | | 4 |
| EN Low Threshold | VENL | 0.9 | 1 | 1.1 | V | | 4 |
| Oscillator Frequency Program Range | fOSC,RNG | 300 | | 2200 | kHz | RFS=45.6k~360k | 4 |
| Oscillator Frequency Accuracy | fOSC,ACC | -12 | | 12 | % | fOSC=2MHz, with RFS resistor of 1% accuracy | 4 |
| Soft-start Time | tSS | 0.5 | 1 | 2 | ms | | 4 |
| Input Voltage (Absolute Maximum), IN to GND | | -0.3 | | 44 | V | | 3 |
| Voltage on LX, FB, EN, FS, PG to GND | | -0.3 | | 44 | V | | 3 |
| BS-LX Voltage | | | | 4 | V | | 3 |
| Power Dissipation | PD | | | 2.5 | W | TA = 25°C, SO8E | 3 |
| Junction Temperature Range | | -40 | | 150 | °C | | 3 |
| Lead Temperature (Soldering) | | | | 260 | °C | 10 sec soldering | 3 |
| Storage Temperature Range | | -65 | | 150 | °C | | 3 |
| Supply Input Voltage | | 4.2 | | 40 | V | | 3 |
| Ambient Temperature Range | | -40 | | 125 | °C | | 3 |
| Package Thermal Resistance, junction-to-ambient | θJA | | 40 | | °C/W | Note 2: measured in natural convection at TA=25°C, two-layer Silergy demo board | 3 |
| Package Thermal Resistance, junction-to-case | θJC | | 12 | | °C/W | | 3 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | 3) The PCB copper area associated with the LX pin | 9 |
## CAD (KiCad official)
- Symbol: `SA24403FCA`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`
- 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files: `sa24403fca-etched.step` / `sa24403fca-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sa24403fca.step` / `sa24403fca.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Silergy Corp datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590904339055652864) (13 pp, sha256 `8ba79a1eb4c8bf1c`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sa24403fca-datasheet.pdf)