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S4MF03107SPZQQ1R

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Texas Instruments Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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S4MF03107SPZQQ1R

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

S4MF03107SPZQQ1R from Texas Instruments, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MibSPI2SCS[0] bidirectional MibSPI2 slave chip select 0, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
2 MibSPI2SCS[1] bidirectional MibSPI2 slave chip select 1, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
3 MibSPI2SCS[2] bidirectional MibSPI2 slave chip select 2, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
4 MibSPI2SCS[3] bidirectional MibSPI2 slave chip select 3, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
5 GIOA[4]/INT[4] bidirectional General-purpose input/output with interrupt capability (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
6 GIOA[5]/INT[5] bidirectional General-purpose input/output with interrupt capability (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
7 CAN1STX bidirectional DCAN1 transmit pin or GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
8 CAN1SRX bidirectional DCAN1 receive pin or GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
9 VSS power_in Digital I/O and core supply ground reference.
10 OSCIN input Crystal connection pin or external clock input (1.55-V).
11 OSCOUT output External crystal connection pin (1.55-V).
12 VCC power_in 1.55-V core supply: Vreg output when the regulator is enabled, VCC input when it is disabled.
13 VSS power_in Digital I/O and core supply ground reference.
14 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
15 GIOA[6]/INT[6] bidirectional General-purpose input/output with interrupt capability (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
16 GIOA[7]/INT[7] bidirectional General-purpose input/output with interrupt capability (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
17 MibSPI2CLK bidirectional MibSPI2 clock, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
18 MibSPI2SIMO bidirectional MibSPI2 slave in/master out data stream, programmable as a GIO pin.
19 MibSPI2SOMI bidirectional MibSPI2 slave out/master in data stream, programmable as a GIO pin.
20 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
21 VSS power_in Digital I/O and core supply ground reference.
22 LIN1SCI1TX bidirectional LIN/SCI1 data transmit, can be programmed as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
23 LIN1SCI1RX bidirectional LIN/SCI1 data receive, can be programmed as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
24 LIN2SCI2TX bidirectional LIN/SCI2 data transmit, can be programmed as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
25 LIN2SCI2RX bidirectional LIN/SCI2 data receive, can be programmed as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
26 MIBSPI1SCS[7] bidirectional MIBSPI1 slave chip select 7, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
27 MIBSPI1SCS[6] bidirectional MIBSPI1 slave chip select 6, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
28 MIBSPI1SCS[5] bidirectional MIBSPI1 slave chip select 5, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
29 MIBSPI1SCS[4] bidirectional MIBSPI1 slave chip select 4, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
30 MIBSPI1SCS[3] bidirectional MIBSPI1 slave chip select 3, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
31 MIBSPI1SCS[2] bidirectional MIBSPI1 slave chip select 2, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
32 MIBSPI1SCS[1] bidirectional MIBSPI1 slave chip select 1, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
33 MIBSPI1SCS[0] bidirectional MIBSPI1 slave chip select 0, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
34 MIBSPI1CLK bidirectional MIBSPI1 clock, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
35 MIBSPI1SIMO bidirectional MIBSPI1 slave in/master out data stream, programmable as a GIO pin.
36 MIBSPI1SOMI bidirectional MIBSPI1 slave out/master in data stream, programmable as a GIO pin.
37 CAN2STX bidirectional DCAN2 transmit pin or GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
38 CAN2SRX bidirectional DCAN2 receive pin or GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
39 HET[0] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
40 HET[1] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
41 VCC power_in 1.55-V core supply: Vreg output when the regulator is enabled, VCC input when it is disabled.
42 VSS power_in Digital I/O and core supply ground reference.
43 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
44 TCK input JTAG test clock that controls the test hardware (3.3-V input, IPD 100 µA).
45 TDO output JTAG test data out, outputs serial data from the test instruction, test data and identification registers (IPD 100 µA).
46 TDI input JTAG test data in, inputs serial data to the test instruction and test data registers (IPU 100 µA).
47 TMS input JTAG serial input controlling the state of the CPU test access port (TAP) controller (IPU 100 µA).
48 TRST input Test hardware reset to TAP, IEEE 1149.1 (JTAG) boundary-scan logic (3.3-V input, IPD 100 µA).
49 HET[2] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
50 HET[3] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
51 VSS power_in Digital I/O and core supply ground reference.
52 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
53 HET[4] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
54 HET[5] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
55 HET[6] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
56 HET[7] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
57 HET[8] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
58 HET[9] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
59 HET[10] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
60 HET[11] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
61 HET[12] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
62 HET[13] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
63 HET[14] bidirectional High-end timer input capture or output compare, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
64 HET[15]/ECLK2 bidirectional HET channel 15 muxed with ECLK2 output; when ECLK2 is enabled via SYSPC1, ECLK2 is output here and HET[15] becomes internal only.
65 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
66 VSS power_in Digital I/O and core supply ground reference.
67 VCC power_in 1.55-V core supply: Vreg output when the regulator is enabled, VCC input when it is disabled.
68 ADEVT bidirectional MibADC event input, can be programmed as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
69 ADIN[0] input MibADC analog input pin (3.3 V).
70 ADIN[1] input MibADC analog input pin (3.3 V).
71 ADIN[2] input MibADC analog input pin (3.3 V).
72 ADIN[3] input MibADC analog input pin (3.3 V).
73 ADIN[4] input MibADC analog input pin (3.3 V).
74 ADIN[5] input MibADC analog input pin (3.3 V).
75 ADIN[6] input MibADC analog input pin (3.3 V).
76 ADIN[7] input MibADC analog input pin (3.3 V).
77 ADIN[8] input MibADC analog input pin (3.3 V).
78 ADIN[9] input MibADC analog input pin (3.3 V).
79 ADIN[10] input MibADC analog input pin (3.3 V).
80 ADIN[11] input MibADC analog input pin (3.3 V).
81 ADIN[12] input MibADC analog input pin (3.3 V).
82 ADREFHI input MibADC module high-voltage reference input (3.3-V REF).
83 ADREFLO input MibADC module low-voltage reference input (GND REF).
84 VSSAD power_in MibADC analog ground reference.
85 VCCAD power_in MibADC analog supply voltage (3.3 V).
86 ADIN[13] input MibADC analog input pin (3.3 V).
87 ADIN[14] input MibADC analog input pin (3.3 V).
88 ADIN[15] input MibADC analog input pin (3.3 V).
89 PORRST input Input master chip power-up reset; external VCC monitor circuitry must assert a power-on reset (3.3-V input, IPD 100 µA).
90 MibSPI2ENA bidirectional MibSPI2 enable pin, can be programmed as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPU 100 µA).
91 ENZ input Enables internal voltage regulator at 0 V and disables it at 3.3 V; provided for testing, not for disabling the regulator in application use (IPD 100 µA).
92 VCC power_in 1.55-V core supply: Vreg output when the regulator is enabled, VCC input when it is disabled.
93 VSS power_in Digital I/O and core supply ground reference.
94 VCCIOR power_in 3.3-V digital I/O and internal regulator supply voltage.
95 VCCP power_in Flash external pump voltage (3.3 V), required for Flash read, program and erase operations (VCCP1 and VCCP2 double bonded to this pin).
96 ECLK bidirectional Bidirectional external clock pin, programmable as a GIO pin (3.3-V adaptive impedance 4 mA I/O, IPD 100 µA).
97 TEST input Test enable reserved for internal use only; TI recommends connecting to ground or pulling down with an external resistor (IPD 100 µA).
98 RST bidirectional Bidirectional reset with open-drain output (drives low only); TI recommends an external pullup resistor (IPU 100 µA).
99 FLTP1 passive Flash Test Pad 1; must connect only to a test pad (not exposed in the final product) or be left unconnected.
100 VSS power_in Digital I/O and core supply ground reference.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

CAD (KiCad official)

  • Symbol: S4MF03107SPZQQ1R
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: s4mf03107spzqq1r-etched.step / s4mf03107spzqq1r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); s4mf03107spzqq1r.step / s4mf03107spzqq1r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (71 pp, sha256 b26b6828cf4d2894, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF