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S3G-E3
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Vishay Intertech Diodes - General Purpose, DO-214AB. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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S3G-E3
Vishay Intertech · Diodes - General Purpose · DO-214AB
S3G-E3 from Vishay Intertech, in a DO-214AB. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Cathode | passive | Cathode terminal, identified by the color band on the package (the band denotes the cathode end); the S3G is rated for a maximum recurrent peak reverse voltage VRRM of 400 V. |
| 2 | Anode | passive | Anode terminal, opposite the cathode band; the device is rated for a maximum average forward rectified current IF(AV) of 3.0 A at TL = 103 °C and an operating junction and storage temperature range of -55 to +150 °C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | DO-214AB |
| Category | Diodes |
| Pins | 2 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum DC reverse current at rated DC blocking voltage | IR | 10 | μA | TA = 25 °C, at rated DC blocking voltage | 2 | ||
| Maximum DC reverse current at rated DC blocking voltage | IR | 250 | μA | TA = 125 °C, at rated DC blocking voltage | 2 | ||
| Maximum instantaneous forward voltage | VF | 1.15 | V | 2.5 A | 2 | ||
| Maximum recurrent peak reverse voltage | VRRM | 400 | V | 1 | |||
| Maximum RMS voltage | VRMS | 280 | V | 1 | |||
| Maximum DC blocking voltage | VDC | 400 | V | 1 | |||
| Maximum average forward rectified current | IF(AV) | 3 | A | TL = 103 °C | 1 | ||
| Peak forward surge current | IFSM | 100 | A | 8.3 ms single half sine-wave superimposed on rated load | 1 | ||
| Operating junction and storage temperature range | TJ, TSTG | -55 | 150 | °C | 1 | ||
| Typical thermal resistance, junction to ambient | RθJA | 47 | °C/W | Mounted on PCB with 0.3" x 0.3" (8.0 mm x 8.0 mm) copper pad area | 2 | ||
| Typical thermal resistance, junction to lead | RθJL | 13 | °C/W | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Terminals: matte tin plated leads, solderable per J-STD-002 and JESD 22-B102 | 1 |
CAD (KiCad official)
- Symbol:
S3G-E3 - Footprint:
Diode_SMD:D_SMC - 3D model: DO-214AB (KiCad packages3D, STEP)
- 3D model files:
s3g-e3-etched.step/s3g-e3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);s3g-e3.step/s3g-e3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (4 pp, sha256
0f6ac455eae8a2a1, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# S3G-E3
**Vishay Intertech** · Diodes - General Purpose · DO-214AB
S3G-E3 from Vishay Intertech, in a DO-214AB. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Cathode | passive | Cathode terminal, identified by the color band on the package (the band denotes the cathode end); the S3G is rated for a maximum recurrent peak reverse voltage VRRM of 400 V. |
| 2 | Anode | passive | Anode terminal, opposite the cathode band; the device is rated for a maximum average forward rectified current IF(AV) of 3.0 A at TL = 103 °C and an operating junction and storage temperature range of -55 to +150 °C. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | DO-214AB |
| Category | Diodes |
| Pins | 2 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum DC reverse current at rated DC blocking voltage | IR | | | 10 | μA | TA = 25 °C, at rated DC blocking voltage | 2 |
| Maximum DC reverse current at rated DC blocking voltage | IR | | | 250 | μA | TA = 125 °C, at rated DC blocking voltage | 2 |
| Maximum instantaneous forward voltage | VF | | | 1.15 | V | 2.5 A | 2 |
| Maximum recurrent peak reverse voltage | VRRM | | | 400 | V | | 1 |
| Maximum RMS voltage | VRMS | | | 280 | V | | 1 |
| Maximum DC blocking voltage | VDC | | | 400 | V | | 1 |
| Maximum average forward rectified current | IF(AV) | | | 3 | A | TL = 103 °C | 1 |
| Peak forward surge current | IFSM | | | 100 | A | 8.3 ms single half sine-wave superimposed on rated load | 1 |
| Operating junction and storage temperature range | TJ, TSTG | -55 | | 150 | °C | | 1 |
| Typical thermal resistance, junction to ambient | RθJA | | 47 | | °C/W | Mounted on PCB with 0.3" x 0.3" (8.0 mm x 8.0 mm) copper pad area | 2 |
| Typical thermal resistance, junction to lead | RθJL | | 13 | | °C/W | | 2 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | Terminals: matte tin plated leads, solderable per J-STD-002 and JESD 22-B102 | 1 |
## CAD (KiCad official)
- Symbol: `S3G-E3`
- Footprint: `Diode_SMD:D_SMC`
- 3D model: DO-214AB (KiCad packages3D, STEP)
- 3D model files: `s3g-e3-etched.step` / `s3g-e3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `s3g-e3.step` / `s3g-e3.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590233600999256064) (4 pp, sha256 `0f6ac455eae8a2a1`, retrieved 2026-10-16, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/s3g-e3-datasheet.pdf)