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S15V06S

HL · MOSFETs · SOP-8

S15V06S from HL, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source terminal of MOSFET 1; the device is rated for VDSS 60 V and continuous drain current 15 A at TC=25℃.
2 G1 input Gate of MOSFET 1; gate-source voltage is rated ±20 V (VGSS).
3 S2 passive Source terminal of MOSFET 2; the device is rated for VDSS 60 V and continuous drain current 15 A at TC=25℃.
4 G2 input Gate of MOSFET 2; gate-source voltage is rated ±20 V (VGSS).
5 D2 passive Drain terminal of MOSFET 2 (pins 5 and 6 are both D2); drain-source voltage is rated 60 V (VDSS).
6 D2 passive Drain terminal of MOSFET 2 (pins 5 and 6 are both D2); drain-source voltage is rated 60 V (VDSS).
7 D1 passive Drain terminal of MOSFET 1 (pins 7 and 8 are both D1); drain-source voltage is rated 60 V (VDSS).
8 D1 passive Drain terminal of MOSFET 1 (pins 7 and 8 are both D1); drain-source voltage is rated 60 V (VDSS).

Key specifications

Parameter Value
Manufacturer HL
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: S15V06S
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: s15v06s-etched.step / s15v06s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); s15v06s.step / s15v06s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HL datasheet (6 pp, sha256 f22cd8853bd069ff, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF