component
S-LMUN5114DW1T1G
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LRC Digital Transistors, SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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S-LMUN5114DW1T1G
LRC · Digital Transistors · SOT-363
S-LMUN5114DW1T1G from LRC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E2 | passive | Emitter of transistor Q2 (PNP BRT); Q1/Q2 ratings are VCBO and VCEO -50 Vdc, IC -100 mAdc. |
| 2 | B2 | passive | Base of Q2, driven through its integrated series base resistor R1 with base-emitter resistor R2. |
| 3 | C1 | passive | Collector of transistor Q1, rated for IC -100 mAdc and VCEO -50 Vdc. |
| 4 | E1 | passive | Emitter of transistor Q1 (PNP BRT); Q1/Q2 ratings are VCBO and VCEO -50 Vdc, IC -100 mAdc. |
| 5 | B1 | passive | Base of Q1, driven through its integrated series base resistor R1 with base-emitter resistor R2. |
| 6 | C2 | passive | Collector of transistor Q2, rated for IC -100 mAdc and VCEO -50 Vdc. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Collector-Base Cutoff Current | ICBO | -100 | nAdc | VCB = -50 V, IE = 0 | 2 | ||
| Collector-Emitter Cutoff Current | ICEO | -500 | nAdc | VCE = -50 V, IB = 0 | 2 | ||
| Emitter-Base Cutoff Current | IEBO | -0.2 | mAdc | VEB = -6.0 V, IC = 0 | 2 | ||
| Collector-Base Breakdown Voltage | V(BR)CBO | -50 | Vdc | IC = -10 A, IE = 0 | 2 | ||
| Collector-Emitter Breakdown Voltage | V(BR)CEO | -50 | Vdc | IC = -2.0 mA, IB = 0 | 2 | ||
| Collector-Emitter Saturation Voltage | VCE(sat) | -0.25 | Vdc | IC = -10 mA, IB = -0.3 mA | 3 | ||
| Output Voltage (off) | VOH | -4.9 | Vdc | VCC = -5.0 V, VB = -0.5 V, RL = 1.0 k | 3 | ||
| Input Resistor R1 | R1 | 7 | 10 | 13 | k | 4 | |
| Resistor Ratio R1/R2 | R1/R2 | 0.17 | 0.21 | 0.25 | 4 | ||
| Total Device Dissipation (one junction heated) | PD | 187 | mW | TA = 25°C, FR-4 @ Minimum Pad (Note 1) | 1 | ||
| Total Device Dissipation (one junction heated) | PD | 256 | mW | TA = 25°C, FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | ||
| Total Device Dissipation (both junctions heated) | PD | 250 | mW | TA = 25°C, FR-4 @ Minimum Pad (Note 1) | 1 | ||
| Total Device Dissipation (both junctions heated) | PD | 385 | mW | TA = 25°C, FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | ||
| Thermal Resistance, Junction-to-Ambient (one junction heated) | RθJA | 670 | °C/W | FR-4 @ Minimum Pad (Note 1) | 1 | ||
| Thermal Resistance, Junction-to-Ambient (one junction heated) | RθJA | 490 | °C/W | FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | ||
| Thermal Resistance, Junction-to-Ambient (both junctions heated) | RθJA | 493 | °C/W | FR-4 @ Minimum Pad (Note 1) | 1 | ||
| Thermal Resistance, Junction-to-Ambient (both junctions heated) | RθJA | 325 | °C/W | FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | ||
| Thermal Resistance, Junction-to-Lead (both junctions heated) | RθJL | 188 | °C/W | FR-4 @ Minimum Pad (Note 1) | 1 | ||
| Thermal Resistance, Junction-to-Lead (both junctions heated) | RθJL | 208 | °C/W | FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 | ||
| Collector-Base Voltage | VCBO | -50 | Vdc | Common for Q1 and Q2, TA = 25°C | 1 | ||
| Collector-Emitter Voltage | VCEO | -50 | Vdc | Common for Q1 and Q2, TA = 25°C | 1 | ||
| Collector Current | IC | -100 | mAdc | Common for Q1 and Q2, TA = 25°C | 1 | ||
| Junction and Storage Temperature | TJ, Tstg | -55 | 150 | °C | 1 |
CAD (KiCad official)
- Symbol:
S-LMUN5114DW1T1G - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files:
s-lmun5114dw1t1g-etched.step/s-lmun5114dw1t1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);s-lmun5114dw1t1g.step/s-lmun5114dw1t1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (19 pp, sha256
948bc022ffd8a38d, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# S-LMUN5114DW1T1G
**LRC** · Digital Transistors · SOT-363
S-LMUN5114DW1T1G from LRC, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E2 | passive | Emitter of transistor Q2 (PNP BRT); Q1/Q2 ratings are VCBO and VCEO -50 Vdc, IC -100 mAdc. |
| 2 | B2 | passive | Base of Q2, driven through its integrated series base resistor R1 with base-emitter resistor R2. |
| 3 | C1 | passive | Collector of transistor Q1, rated for IC -100 mAdc and VCEO -50 Vdc. |
| 4 | E1 | passive | Emitter of transistor Q1 (PNP BRT); Q1/Q2 ratings are VCBO and VCEO -50 Vdc, IC -100 mAdc. |
| 5 | B1 | passive | Base of Q1, driven through its integrated series base resistor R1 with base-emitter resistor R2. |
| 6 | C2 | passive | Collector of transistor Q2, rated for IC -100 mAdc and VCEO -50 Vdc. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-363 |
| Category | Transistors/Thyristors |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Collector-Base Cutoff Current | ICBO | | | -100 | nAdc | VCB = -50 V, IE = 0 | 2 |
| Collector-Emitter Cutoff Current | ICEO | | | -500 | nAdc | VCE = -50 V, IB = 0 | 2 |
| Emitter-Base Cutoff Current | IEBO | | | -0.2 | mAdc | VEB = -6.0 V, IC = 0 | 2 |
| Collector-Base Breakdown Voltage | V(BR)CBO | -50 | | | Vdc | IC = -10 A, IE = 0 | 2 |
| Collector-Emitter Breakdown Voltage | V(BR)CEO | -50 | | | Vdc | IC = -2.0 mA, IB = 0 | 2 |
| Collector-Emitter Saturation Voltage | VCE(sat) | | | -0.25 | Vdc | IC = -10 mA, IB = -0.3 mA | 3 |
| Output Voltage (off) | VOH | -4.9 | | | Vdc | VCC = -5.0 V, VB = -0.5 V, RL = 1.0 k | 3 |
| Input Resistor R1 | R1 | 7 | 10 | 13 | k | | 4 |
| Resistor Ratio R1/R2 | R1/R2 | 0.17 | 0.21 | 0.25 | | | 4 |
| Total Device Dissipation (one junction heated) | PD | | | 187 | mW | TA = 25°C, FR-4 @ Minimum Pad (Note 1) | 1 |
| Total Device Dissipation (one junction heated) | PD | | | 256 | mW | TA = 25°C, FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 |
| Total Device Dissipation (both junctions heated) | PD | | | 250 | mW | TA = 25°C, FR-4 @ Minimum Pad (Note 1) | 1 |
| Total Device Dissipation (both junctions heated) | PD | | | 385 | mW | TA = 25°C, FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 |
| Thermal Resistance, Junction-to-Ambient (one junction heated) | RθJA | | | 670 | °C/W | FR-4 @ Minimum Pad (Note 1) | 1 |
| Thermal Resistance, Junction-to-Ambient (one junction heated) | RθJA | | | 490 | °C/W | FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 |
| Thermal Resistance, Junction-to-Ambient (both junctions heated) | RθJA | | | 493 | °C/W | FR-4 @ Minimum Pad (Note 1) | 1 |
| Thermal Resistance, Junction-to-Ambient (both junctions heated) | RθJA | | | 325 | °C/W | FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 |
| Thermal Resistance, Junction-to-Lead (both junctions heated) | RθJL | | | 188 | °C/W | FR-4 @ Minimum Pad (Note 1) | 1 |
| Thermal Resistance, Junction-to-Lead (both junctions heated) | RθJL | | | 208 | °C/W | FR-4 @ 1.0 x 1.0 inch Pad (Note 2) | 1 |
| Collector-Base Voltage | VCBO | -50 | | | Vdc | Common for Q1 and Q2, TA = 25°C | 1 |
| Collector-Emitter Voltage | VCEO | -50 | | | Vdc | Common for Q1 and Q2, TA = 25°C | 1 |
| Collector Current | IC | -100 | | | mAdc | Common for Q1 and Q2, TA = 25°C | 1 |
| Junction and Storage Temperature | TJ, Tstg | -55 | | 150 | °C | | 1 |
## CAD (KiCad official)
- Symbol: `S-LMUN5114DW1T1G`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files: `s-lmun5114dw1t1g-etched.step` / `s-lmun5114dw1t1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `s-lmun5114dw1t1g.step` / `s-lmun5114dw1t1g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590917086384640000) (19 pp, sha256 `948bc022ffd8a38d`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/s-lmun5114dw1t1g-datasheet.pdf)