component
S-LESD8L3.3CT5G
Public Made by Adomby adom
LRC ESD And Surge Protection (TVS/ESD), SOD-882. Unpolarised two-terminal part: the datasheet prints no pin numbers, so pins 1 and 2 follow the library convention, KiCad symbol/footprint/3D.
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S-LESD8L3.3CT5G
LRC · ESD And Surge Protection (TVS/ESD) · SOD-882
S-LESD8L3.3CT5G from LRC, in a SOD-882. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | K | passive | Cathode: the banded/marked end per the datasheet; pad 1 of the KiCad diode footprint. |
| 2 | A | passive | Anode. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOD-882 |
| Category | Circuit Protection |
| Pins | 2 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IEC 61000-4-2 ESD contact voltage | -10 | 10 | kV | IEC 61000-4-2 contact | 1 | ||
| IEC 61000-4-2 ESD air voltage | -15 | 15 | kV | IEC 61000-4-2 air | 1 | ||
| Maximum reverse leakage current | IR | 50 | nA | @ VRWM | 2 | ||
| Breakdown voltage | VBR | 3.8 | V | @ IT (pulse test, Note 2) | 2 | ||
| Clamping voltage | VC | 15 | V | @ IPPM = 2 A (Note 3) | 2 | ||
| Capacitance | C | 0.9 | pF | @ VR = 0 and f = 1.0 MHz | 2 | ||
| Forward voltage | VF | 1 | V | @ IF = 10 mA | 2 | ||
| Total power dissipation on FR-5 board | PD | 150 | mW | on FR-5 Board (Note 1) @ TA = 25°C | 1 | ||
| Storage temperature range | Tstg | -55 | 150 | °C | 1 | ||
| Junction temperature range | TJ | -55 | 125 | °C | 1 | ||
| Lead solder temperature maximum | TL | 260 | °C | 10 second duration | 1 | ||
| Working peak reverse voltage | VRWM | 3.3 | V | 2 | |||
| Test current | IT | 1 | mA | 2 |
CAD (KiCad official)
- Symbol:
S-LESD8L3.3CT5G - Footprint:
Diode_SMD:D_SOD-882 - 3D model: SOD-882 (KiCad packages3D, STEP)
- 3D model files:
s-lesd8l3-3ct5g-etched.step/s-lesd8l3-3ct5g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);s-lesd8l3-3ct5g.step/s-lesd8l3-3ct5g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (5 pp, sha256
d6d58d7be131cdc5, retrieved 2026-10-26, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins, primarycathode-band convention(convention), consensusoff(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# S-LESD8L3.3CT5G
**LRC** · ESD And Surge Protection (TVS/ESD) · SOD-882
S-LESD8L3.3CT5G from LRC, in a SOD-882. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | K | passive | Cathode: the banded/marked end per the datasheet; pad 1 of the KiCad diode footprint. |
| 2 | A | passive | Anode. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOD-882 |
| Category | Circuit Protection |
| Pins | 2 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IEC 61000-4-2 ESD contact voltage | | -10 | | 10 | kV | IEC 61000-4-2 contact | 1 |
| IEC 61000-4-2 ESD air voltage | | -15 | | 15 | kV | IEC 61000-4-2 air | 1 |
| Maximum reverse leakage current | IR | | | 50 | nA | @ VRWM | 2 |
| Breakdown voltage | VBR | 3.8 | | | V | @ IT (pulse test, Note 2) | 2 |
| Clamping voltage | VC | | | 15 | V | @ IPPM = 2 A (Note 3) | 2 |
| Capacitance | C | | | 0.9 | pF | @ VR = 0 and f = 1.0 MHz | 2 |
| Forward voltage | VF | | | 1 | V | @ IF = 10 mA | 2 |
| Total power dissipation on FR-5 board | PD | | | 150 | mW | on FR-5 Board (Note 1) @ TA = 25°C | 1 |
| Storage temperature range | Tstg | -55 | | 150 | °C | | 1 |
| Junction temperature range | TJ | -55 | | 125 | °C | | 1 |
| Lead solder temperature maximum | TL | | | 260 | °C | 10 second duration | 1 |
| Working peak reverse voltage | VRWM | | 3.3 | | V | | 2 |
| Test current | IT | | 1 | | mA | | 2 |
## CAD (KiCad official)
- Symbol: `S-LESD8L3.3CT5G`
- Footprint: `Diode_SMD:D_SOD-882`
- 3D model: SOD-882 (KiCad packages3D, STEP)
- 3D model files: `s-lesd8l3-3ct5g-etched.step` / `s-lesd8l3-3ct5g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `s-lesd8l3-3ct5g.step` / `s-lesd8l3-3ct5g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [LRC datasheet](docs/s-lesd8l3-3ct5g-datasheet.pdf) (5 pp, sha256 `d6d58d7be131cdc5`, retrieved 2026-10-26, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins`, primary `cathode-band convention` (convention), consensus `off` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/s-lesd8l3-3ct5g-datasheet.pdf)