component
S-LESD32L05T1G
Public Made by Adomby adom
LRC Digital Transistors, SOT-323. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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S-LESD32L05T1G
LRC · Digital Transistors · SOT-323
S-LESD32L05T1G from LRC, in a SOT-323. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | Protected line pin 1 (diode anode in the page 1 schematic) with working reverse stand-off voltage VRWM of 5 V max and junction capacitance of 0.8 pF max at VR=0 V, f=1 MHz. |
| 2 | I/O2 | passive | Protected line pin 2 (diode anode in the page 1 schematic) with working reverse stand-off voltage VRWM of 5 V max and junction capacitance of 0.8 pF max at VR=0 V, f=1 MHz. |
| 3 | COMMON | passive | Common node of the two diodes (cathodes) in the page 1 schematic, which gives IEC 61000-4-2 protection of ±30 kV contact and ±30 kV air discharge. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-323 |
| Category | Transistors/Thyristors |
| Pins | 3 |
CAD (KiCad official)
- Symbol:
S-LESD32L05T1G - Footprint:
Package_TO_SOT_SMD:SOT-323_SC-70 - 3D model: SOT-323 (KiCad packages3D, STEP)
- 3D model files:
s-lesd32l05t1g-etched.step/s-lesd32l05t1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);s-lesd32l05t1g.step/s-lesd32l05t1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (5 pp, sha256
25fb051946be607f, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# S-LESD32L05T1G
**LRC** · Digital Transistors · SOT-323
S-LESD32L05T1G from LRC, in a SOT-323. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | Protected line pin 1 (diode anode in the page 1 schematic) with working reverse stand-off voltage VRWM of 5 V max and junction capacitance of 0.8 pF max at VR=0 V, f=1 MHz. |
| 2 | I/O2 | passive | Protected line pin 2 (diode anode in the page 1 schematic) with working reverse stand-off voltage VRWM of 5 V max and junction capacitance of 0.8 pF max at VR=0 V, f=1 MHz. |
| 3 | COMMON | passive | Common node of the two diodes (cathodes) in the page 1 schematic, which gives IEC 61000-4-2 protection of ±30 kV contact and ±30 kV air discharge. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOT-323 |
| Category | Transistors/Thyristors |
| Pins | 3 |
## CAD (KiCad official)
- Symbol: `S-LESD32L05T1G`
- Footprint: `Package_TO_SOT_SMD:SOT-323_SC-70`
- 3D model: SOT-323 (KiCad packages3D, STEP)
- 3D model files: `s-lesd32l05t1g-etched.step` / `s-lesd32l05t1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `s-lesd32l05t1g.step` / `s-lesd32l05t1g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [LRC datasheet](docs/s-lesd32l05t1g-datasheet.pdf) (5 pp, sha256 `25fb051946be607f`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/s-lesd32l05t1g-datasheet.pdf)