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S-LDTD113ZLT1G

Public Made by Adom

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LRC Digital Transistors, TO-236. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttriode-mos tube-transistors-ldtd113zlt1gfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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S-LDTD113ZLT1G

LRC · Digital Transistors · TO-236

S-LDTD113ZLT1G from LRC, in a TO-236. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Base input Base (input) of the NPN transistor with built-in R1 1 kΩ series bias resistor; input voltage Vin rated -5 to +10 V, Vi(on) min 1.5 V, Vi(off) max 0.3 V.
2 Emitter passive Emitter of the NPN transistor, connected through R2 (10 kΩ) to the base network; typically tied to ground.
3 Collector passive Collector (output) of the NPN transistor with VCEO and VCBO of 50 V and IC max 500 mA.

Key specifications

Parameter Value
Manufacturer LRC
Package TO-236
Category Triode/MOS Tube/Transistor
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Collector-Emitter Breakdown Voltage VBR(CEO) 50 V IC = 1 mA, IB = 0 2
Collector-Base Breakdown Voltage VBR(CBO) 50 V IC = 100 μA, IE = 0 2
Collector-Base Cutoff Current ICBO 500 nA VCB = 50 V, IE = 0 2
Emitter-Base Cutoff Current IEBO 7.2 mA VEB = 5.0 V, IC = 0 2
Collector-Emitter Cutoff Current ICEO 1 μA VCE = 50 V, IB = 0 2
DC Current Gain HFE 82 IC = 50 mA, VCE = 5 V 2
Collector-Emitter Saturation Voltage VCE(sat) 0.3 V IC = 50 mA, IB = 2.5 mA 2
Input Voltage (off) Vi(off) 0.3 V VCE = 5.0 V, IC = 100 μA 2
Input Voltage (on) Vi(on) 1.5 V VCE = 0.3 V, IC = 20 mA 2
Output Voltage (on) VOL 0.3 V VCC = 5.0 V, VB = 3 V, RL = 1.0KΩ 2
Output Voltage (off) VOH 3 V VCC = 5.0 V, VB = 0.3 V, RL = 1.0KΩ 2
Input Resistor R1 0.7 1 1.3 KΩ 2
Resistor Ratio R2/R1 8 10 12 2
Collector-Emitter Voltage VCEO 50 V Ta = 25ºC 1
Collector-Base Voltage VCBO 50 V Ta = 25ºC 1
Collector Current IC 500 mA Ta = 25ºC 1
Input Voltage Vin -5 10 V Ta = 25ºC 1
Total Device Dissipation PD 225 mW FR-5 Board (Note 1) @ TA = 25ºC 1
Derate above 25ºC 1.8 mW/ºC FR-5 Board (Note 1) 1
Thermal Resistance, Junction-to-Ambient RΘJA 556 ºC/W Note 1 (FR-5 = 1.0×0.75×0.062 in.) 1
Junction and Storage Temperature TJ, Tstg -55 150 ºC 1

CAD (KiCad official)

  • Symbol: S-LDTD113ZLT1G
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: TO-236 (KiCad packages3D, STEP)
  • 3D model files: s-ldtd113zlt1g-etched.step / s-ldtd113zlt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); s-ldtd113zlt1g.step / s-ldtd113zlt1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (4 pp, sha256 a2b2570e8737dc35, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF