component
RY3740CT5
Public Made by Adomby adom
RYCHIP DC-DC Converters, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownRY3740CT5
RYCHIP · DC-DC Converters · SOT-23-5
RY3740CT5 from RYCHIP, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Power switch output: the drain of the internal MOSFET switch, to which the power inductor and output rectifier connect; SW can swing between GND and 35V. |
| 2 | GND | power_in | Ground pin. |
| 3 | FB | input | Feedback reference voltage pin: a resistor in series between WLED and ground acts as the current sense, and the sensed feedback voltage (0.25V for the CT5 variant) sets the LED current. |
| 4 | CTRL | input | Multi-function pin for boost enable control and PWM dimming; it should not be left floating, and the PWM magnitude must be higher than the minimum CTRL enable voltage. |
| 5 | IN | power_in | Input supply pin, which must be locally bypassed; the input range is 2.5V to 5.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RYCHIP |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating junction temperature | -40 | 125 | °C | 4 | |||
| Operating temperature range | -40 | 85 | °C | 4 | |||
| Input voltage | VIN | 2.5 | 5.5 | V | 4 | ||
| Output voltage | VOUT | 34 | V | 4 | |||
| VIN, VCTRL voltage | -0.3 | 6 | V | 3 | |||
| VSW, VOVP voltage | -0.3 | 37 | V | 3 | |||
| VSW, VOVP voltage (10ns transient) | -5 | 38 | V | 10ns transient | 3 | ||
| All other pins | -0.3 | 6 | V | 3 | |||
| Operating junction temperature, TJ | TJ | -40 | 150 | °C | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Lead temperature (soldering, 10 sec) | 260 | °C | 10 sec | 3 | |||
| Input voltage range | 2.5 | 5.5 | V | 5 | |||
| Output voltage range | 34 | V | 5 | ||||
| Supply Current (Quiescent) | 200 | 250 | µA | VFB =110% | 5 | ||
| Supply Current (Shutdown) | 0.1 | 1 | µA | VCTRL =0 or CTRL = GND | 5 | ||
| Feedback Voltage tolerance (1±2.5%) | -2.5 | 2.5 | % | 5 | |||
| SW On Resistance | 400 | 650 | mΩ | 5 | |||
| UVLO Wake up VIN Voltage | 2.3 | 2.5 | V | 5 | |||
| UVLO Shutdown VIN Voltage | 1.7 | 1.9 | V | 5 | |||
| Feedback Voltage | 250 | mV | 5 | ||||
| Internal SW Current Limit | 1.6 | A | 5 | ||||
| OVP Protection Threshold | 35 | V | 5 | ||||
| Switching Frequency | 1.2 | MHz | 5 | ||||
| Maximum Duty Cycle | 85 | % | VFB=90% | 5 | |||
| Minimum On-Time | 80 | ns | 5 | ||||
| EN Rising Threshold | 1.1 | V | 5 | ||||
| EN Falling Threshold | 0.6 | V | 5 | ||||
| UVLO Hysteresis VIN voltage | 400 | mV | 5 | ||||
| Soft Start | 600 | µS | 5 | ||||
| Thermal Shutdown | 160 | ℃ | 5 | ||||
| Thermal Hysteresis | 30 | ℃ | 5 | ||||
| Junction-to-ambient thermal resistance (RθJA) | RθJA | 180 | °C/W | SOT23-5 column; JESD 51-7, 4-layer JEDEC board | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 130 | °C/W | SOT23-5 column; JESD 51-7, 4-layer JEDEC board | 4 | ||
| Junction-to-board thermal resistance | RθJB | 45 | °C/W | SOT23-5 column; JESD 51-7, 4-layer JEDEC board | 4 | ||
| Junction-to-top characterization parameter | ψJT | 35 | °C/W | SOT23-5 column; JESD 51-7, 4-layer JEDEC board | 4 | ||
| Junction-to-board characterization parameter | ψJB | 45 | °C/W | SOT23-5 column; JESD 51-7, 4-layer JEDEC board | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | that connects to GND. The inductor should be placed as close as possible to the SW pin and output capacitor. 2. Minimize the copper area of the switch node. The SW terminals should be directly connect | 12 |
CAD (KiCad official)
- Symbol:
RY3740CT5 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
ry3740ct5-etched.step/ry3740ct5-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ry3740ct5.step/ry3740ct5.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RYCHIP datasheet (16 pp, sha256
aefb3c656d6750d8, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).