component
RTQ2103AGSP-QA
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownRTQ2103AGSP-QA
Richtek Tech · DC-DC Converters · SOP-8-EP
RTQ2103AGSP-QA from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable control input; pull high to enable, with EN high threshold of 1 V minimum and low threshold of 0.4 V maximum. |
| 2 | PGND | power_in | Power ground; the exposed pad must be soldered to a large PCB and connected to PGND for maximum power dissipation. |
| 3 | AGND | power_in | Analog ground that should be electrically connected to GND close to the device. |
| 4 | FB | input | Feedback voltage input connected directly to the feedback resistive divider, with VREF of 0.45 V typical. |
| 5 | VOS | input | Output voltage sense pin for the internal control loop that must be connected to the output. |
| 6 | PGOOD | output | Power good open-drain output that is pulled low when the output voltage is below regulation limits and can be left floating if not used. |
| 7 | LX | output | Switch node that is the source of the internal high-side power MOSFET and the drain of the internal low-side (synchronous) rectifier MOSFET. |
| 8 | VIN | power_in | Power input supply voltage of 3 V to 6 V. |
| 9 | PGND | power_in | Exposed thermal pad that must be soldered to a large PCB and connected to PGND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Under-Voltage Lockout Threshold | VUVLO | 2.35 | 2.52 | V | VCC rising | 4 | |
| Shutdown Supply Current | ISHDN | 2 | μA | EN = 0V | 4 | ||
| Voltage Reference | VREF | 0.443 | 0.45 | 0.457 | V | 4 | |
| Current Limit High-Side Peak Current | ILIM | 2.5 | 3.2 | 4 | A | Peak current | 4 |
| Current Limit Low-Side Valley Current | ILIM | 2 | 2.4 | 3.2 | A | Low-Side Valley current | 4 |
| Power Good Threshold | VPGOODTH | 15 | 10 | 5 | % | VOUT falling referenced to VOUT nominal | 4 |
| Power Good Leakage Current | IPGOOD | 0.01 | 0.1 | μA | VPGOOD = 5V | 4 | |
| Power Good Low Level Voltage | VPGOOD_L | 0.3 | V | Isink = 500μA | 4 | ||
| EN Threshold Voltage H-Level | VENH | 1 | V | EN rising | 4 | ||
| EN Threshold Voltage L-Level | VENL | 0.4 | V | EN falling | 4 | ||
| Thermal Shutdown Temperature | 155 | 175 | °C | 5 | |||
| Switching Frequency | fOSC | 2.2 | 2.7 | 3 | MHz | 5 | |
| Supply Input Voltage (recommended) | VIN | 3 | 6 | V | 4 | ||
| Junction Temperature Range (recommended) | -40 | 150 | °C | 4 | |||
| Ambient Temperature Range (recommended) | -40 | 125 | °C | 4 | |||
| Supply Input Voltage (absolute maximum) | VIN | -0.3 | 7 | V | 4 | ||
| LX Pin Switch Voltage | -0.3 | V | max is (VIN + 0.3V) | 4 | |||
| LX Pin Switch Voltage (<100ns) | -5 | 9 | V | < 100ns | 4 | ||
| Other Pins Voltage | -0.3 | V | max is (VIN + 0.3V) | 4 | |||
| Power Dissipation PD | PD | 4.31 | W | TA = 25°C, SOP-8 (Exposed Pad) | 4 | ||
| Junction Temperature (absolute maximum) | 150 | °C | 4 | ||||
| Lead Temperature (soldering, 10 sec) | 260 | °C | Soldering, 10 sec | 4 | |||
| Storage Temperature Range | -65 | 150 | °C | 4 | |||
| ESD Susceptibility HBM | 2 | kV | HBM (Human Body Model) | 4 | |||
| Package Thermal Resistance, Junction-to-Ambient | θJA | 29 | °C/W | SOP-8 (Exposed Pad), JEDEC 51-7 four-layer board, TA = 25°C | 4 | ||
| Package Thermal Resistance, Junction-to-Case | θJC | 2 | °C/W | SOP-8 (Exposed Pad), measured at exposed pad | 4 |
CAD (KiCad official)
- Symbol:
RTQ2103AGSP-QA - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
rtq2103agsp-qa-etched.step/rtq2103agsp-qa-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rtq2103agsp-qa.step/rtq2103agsp-qa.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (14 pp, sha256
3929c0d0939697f2, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).