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RTL8306MB-CG

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Realtek Semicon Ethernet ICs, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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RTL8306MB-CG

Realtek Semicon · Ethernet ICs · QFN-64-EP(9x9)

RTL8306MB-CG from Realtek Semicon, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDDL power_in Analog power supply pin at 1.0V for the PHY analog circuitry.
2 RXIP2 bidirectional Differential receive data input (positive) for Port 2, supporting 10Base-T and 100Base-TX.
3 RXIN2 bidirectional Differential receive data input (negative) for Port 2, supporting 10Base-T and 100Base-TX.
4 TXON2 bidirectional Differential transmit data output (negative) for Port 2, supporting 10Base-T and 100Base-TX.
5 TXOP2 bidirectional Differential transmit data output (positive) for Port 2, supporting 10Base-T and 100Base-TX.
6 AVDDH power_in Analog power supply pin at 3.3V.
7 TXOP3 bidirectional Differential transmit data output (positive) for Port 3, supporting 10Base-T and 100Base-TX.
8 TXON3 bidirectional Differential transmit data output (negative) for Port 3, supporting 10Base-T and 100Base-TX.
9 RXIN3 bidirectional Differential receive data input (negative) for Port 3, supporting 10Base-T and 100Base-TX.
10 RXIP3 bidirectional Differential receive data input (positive) for Port 3, supporting 10Base-T and 100Base-TX.
11 DVDDL power_in Digital core power supply pin at 1.0V.
12 AVDDL power_in Analog power supply pin at 1.0V for the PHY analog circuitry.
13 RXIP4 bidirectional Differential receive data input (positive) for Port 4, supporting 10Base-T and 100Base-TX.
14 RXIN4 bidirectional Differential receive data input (negative) for Port 4, supporting 10Base-T and 100Base-TX.
15 TXON4 bidirectional Differential transmit data output (negative) for Port 4, supporting 10Base-T and 100Base-TX.
16 TXOP4 bidirectional Differential transmit data output (positive) for Port 4, supporting 10Base-T and 100Base-TX.
17 AVDDH power_in Analog power supply pin at 3.3V.
18 MTXD3 bidirectional (T)MII MAC5 transmit data nibble bit 3 in MAC mode, also P0LED1 and DUP_STA strapping pin; internal pull-down about 75KΩ.
19 MTXD2 bidirectional (T)MII MAC5 transmit data nibble bit 2 in MAC mode, also P1LED1 and SPD_STA strapping pin; internal pull-down about 75KΩ.
20 MTXD1 bidirectional (T)MII MAC5 transmit data nibble bit 1 in MAC mode, also P2LED1 and IF_MODE strapping pin; internal pull-down about 75KΩ.
21 MTXD0 bidirectional (T)MII MAC5 transmit data nibble bit 0 in MAC mode, also P3LED1 and IF_SEL[0] strapping pin; internal pull-down about 75KΩ.
22 MTXEN bidirectional (T)MII MAC5 transmit enable in MAC mode, also EN_LED1 strapping pin; output with internal pull-down about 75KΩ.
23 MTXC/PRXC bidirectional (T)MII MAC5 transmit clock in MAC mode, 25MHz for 100Mbps and 2.5MHz for 10Mbps in MII mode; internal pull-down about 75KΩ.
24 MTXER bidirectional MII MAC5 transmit error output in MII MAC mode, also IF_SEL[1] strapping pin; internal pull-down about 75KΩ.
25 MCOL bidirectional MII MAC5 collision detect input in MII MAC mode; internal pull-down about 75KΩ.
26 DVDDH power_in Digital IO power supply pin at 3.3V.
27 MRXER bidirectional MII MAC5 receive error input in MII MAC mode, or PTXER in PHY mode; not used in TMII and RMII modes.
28 MRXC bidirectional (T)MII MAC5 receive clock input in MAC mode; internal pull-down about 75KΩ.
29 MRXDV input (T)MII MAC5 receive data valid input in MAC mode, used as CRS_DV in RMII mode; internal pull-down about 75KΩ.
30 MRXD0 bidirectional (T)MII MAC5 receive data nibble bit 0 in MAC mode, also P4LED1 pin; internal pull-down about 75KΩ.
31 MRXD1 bidirectional (T)MII MAC5 receive data nibble bit 1 in MAC mode; internal pull-down about 75KΩ.
32 MRXD2 bidirectional (T)MII MAC5 receive data nibble bit 2 in MAC mode; not used in RMII mode; internal pull-down about 75KΩ.
33 MRXD3 bidirectional (T)MII MAC5 receive data nibble bit 3 in MAC mode; not used in RMII mode; internal pull-down about 75KΩ.
34 DVDDL power_in Digital core power supply pin at 1.0V.
35 MII_LINK_STA input Real-time link status input for the MAC5 (T)MII/RMII port, where 0 means link down and 1 means link up; internal pull-down about 75KΩ.
36 INT/FCTRL_STA bidirectional Interrupt output that is pulled low when any interrupt event flag is set, also FCTRL_STA strapping pin; internal pull-up about 75KΩ with 4mA drive.
37 SCL/MDC bidirectional I2C clock for EEPROM auto-load at power-on, then MDC clock for register access; internal pull-up about 75KΩ with 4mA drive.
38 SDA/MDIO bidirectional I2C data for EEPROM auto-load at power-on, then MDIO data for register access; internal pull-up about 75KΩ with 4mA drive.
39 RESETB input System pin reset input, active low; internal pull-up about 75KΩ.
40 SLP_WKP output Output used to power off the CPU for power saving and to power on or wake the CPU on a wakeup event; internal pull-up about 75KΩ with 4mA drive.
41 P0LED0 bidirectional LED0 status output for Port 0, also DIS_EEE strapping input; internal pull-down about 75KΩ with 10mA drive.
42 P1LED0 bidirectional LED0 status output for Port 1, also LED_MODE[1] strapping input; internal pull-down about 75KΩ with 10mA drive.
43 P2LED0 bidirectional LED0 status output for Port 2, also LED_MODE[2] strapping input; internal pull-down about 75KΩ with 10mA drive.
44 DVDDH power_in Digital IO power supply pin at 3.3V.
45 P3LED0 bidirectional LED0 status output for Port 3, also RMAMODE strapping input; internal pull-down about 75KΩ with 10mA drive.
46 P4LED0 bidirectional LED0 status output for Port 4, also UNKOWN_MULTI strapping input; internal pull-down about 75KΩ with 10mA drive.
47 DVDDL power_in Digital core power supply pin at 1.0V.
48 V10OUT output LDO 1.0V output pin generated from the 3.3V input.
49 V33IN power_in LDO 3.3V input pin supplying the internal 1.0V regulator.
50 AVDDHPLL power_in Power supply pin at 3.3V for the PLL.
51 XO output 25MHz crystal clock output; must be left floating when XI is driven by an oscillator.
52 XI input 25MHz crystal clock input with a clock tolerance of ±50ppm; an oscillator may be used here.
53 AVDDLPLL power_in Power supply pin at 1.0V for the PLL.
54 IBREF output PHY bandgap reference pin; a 2.49KΩ (1%) resistor must be connected between IBREF and GND.
55 AVDDL power_in Analog power supply pin at 1.0V for the PHY analog circuitry.
56 RXIP0 bidirectional Differential receive data input (positive) for Port 0, supporting 10Base-T and 100Base-TX.
57 RXIN0 bidirectional Differential receive data input (negative) for Port 0, supporting 10Base-T and 100Base-TX.
58 TXON0 bidirectional Differential transmit data output (negative) for Port 0, supporting 10Base-T and 100Base-TX.
59 TXOP0 bidirectional Differential transmit data output (positive) for Port 0, supporting 10Base-T and 100Base-TX.
60 AVDDH power_in Analog power supply pin at 3.3V.
61 TXOP1 bidirectional Differential transmit data output (positive) for Port 1, supporting 10Base-T and 100Base-TX.
62 TXON1 bidirectional Differential transmit data output (negative) for Port 1, supporting 10Base-T and 100Base-TX.
63 RXIN1 bidirectional Differential receive data input (negative) for Port 1, supporting 10Base-T and 100Base-TX.
64 RXIP1 bidirectional Differential receive data input (positive) for Port 1, supporting 10Base-T and 100Base-TX.
65 E_PAD power_in Exposed pad, the digital ground for the whole chip that must be connected to GND.

Key specifications

Parameter Value
Manufacturer Realtek Semicon
Package QFN-64-EP(9x9)
Category Communication Interface Chip/UART/485/232
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DVDDH, AVDDH, AVDDHPLL Supply Referenced to GND -0.3 3.63 V Referenced to GND; datasheet prints GND-0.3 as min 56
DVDDL, AVDDL, AVDDLPLL Supply Referenced to GND -0.3 1.1 V Referenced to GND; datasheet prints GND-0.3 as min 56
3.3V Vcc Supply Voltage Range (DVDDH, AVDDH, AVDDHPLL) 3.13 3.47 V 56
1.0V Vcc Supply Voltage Range (DVDDL, AVDDL, AVDDLPLL) 0.95 1.05 V 56
Ambient Operating Temperature (Ta) Ta 0 70 C 56
Storage Temperature -55 150 C 56
TTL Input High Voltage Vih 2 V 56
TTL Input Low Voltage Vil 0.8 V 56
TTL Input Current Iin -10 10 µA 56
Output High Voltage Voh 2.25 V 56
Output Low Voltage Vol 0.4 V 56
Output Three State Leakage Current IOZ 10 µA 56
MII MAC mode TXD[3:0]/PRXD[3:0], TXEN/PRXDV setup time to TXC/PRXC rising edge TOS 15 ns 57
MII MAC mode TXD[3:0]/PRXD[3:0], TXEN/PRXDV hold time to TXC/PRXC rising edge TOH 2 ns 57
MII MAC mode RXD[3:0]/PTXD[3:0], RXDV/PTXEN setup time to RXC/PTXC rising edge TIS 4 ns 57
MII MAC mode RXD[3:0]/PTXD[3:0], RXDV/PTXEN hold time to RXC/PTXC rising edge TIH 3 ns 57
MII PHY mode TXD[3:0]/PRXD[3:0], TXEN/PRXDV setup time to TXC/PRXC rising edge TOS 15 ns 58
MII PHY mode TXD[3:0]/PRXD[3:0], TXEN/PRXDV hold time to TXC/PRXC rising edge TOH 15 ns 58
MII PHY mode RXD[3:0]/PTXD[3:0], RXDV/PTXEN setup time to RXC/PTXC rising edge TIS 10 ns 58
MII PHY mode RXD[3:0]/PTXD[3:0], RXDV/PTXEN hold time to RXC/PTXC rising edge TIH 0 ns 58
TMII MAC mode TXD[3:0]/PRXD[3:0], TXEN/PRXDV setup time to TXC/PRXC rising edge TOS 7 ns 58
TMII MAC mode TXD[3:0]/PRXD[3:0], TXEN/PRXDV hold time to TXC/PRXC rising edge TOH 2 ns 58
TMII MAC mode RXD[3:0]/PTXD[3:0], RXDV/PTXEN setup time to RXC/PTXC rising edge TIS 4 ns 58
TMII MAC mode RXD[3:0]/PTXD[3:0], RXDV/PTXEN hold time to RXC/PTXC rising edge TIH 3 ns 58
MDC Clock Cycle Tcyc 400 ns 60
MDIO Input Setup Time to MDC Rising Edge TIS 50 ns 60
MDIO Input Hold Time to MDC Rising Edge TIH 10 ns 60
MDIO Output Delay Time to MDC Rising Edge TD 2 10 ns 60
Data In Hold Time t5 0 ns 61
Data In Setup Time t6 100 ns 61
IBREF reference resistor tolerance -1 1 % 2.49KΩ (1%) resistor between IBREF and GND 15
IBREF reference resistor nominal value 2.49 kΩ Resistor between IBREF and GND 15
Crystal frequency tolerance (external 25 MHz crystal) -50 50 ppm Nominal frequency 25.000 MHz 33
Crystal equivalent series resistance (external crystal) 50 Ohm 33
XTALI/OSC input clock jitter tolerance 250 ps 5KHz to 2.5MHz range 33
Crystal/oscillator input duty cycle 40 60 % 33
Hardware reset pulse width (RESET#) 1 µs Pull RESET# pin low 18

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts silver P: Digital Power Pin AP: Analog Power Pin G: Digital Ground Pin AG: Analog Ground Pin 13

CAD (KiCad official)

  • Symbol: RTL8306MB-CG
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: rtl8306mb-cg-etched.step / rtl8306mb-cg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rtl8306mb-cg.step / rtl8306mb-cg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Realtek Semicon datasheet (63 pp, sha256 0d3f23c1e9494833, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF