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RTL8211EG-VB-CG

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Realtek Semicon Ethernet Transceivers, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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RTL8211EG-VB-CG

Realtek Semicon · Ethernet Transceivers · QFN-64-EP(9x9)

RTL8211EG-VB-CG from Realtek Semicon, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK125 output 125MHz reference clock generated from the internal PLL; keep floating if the MAC does not use it.
2 GND power_in Ground.
3 REG_OUT output Switching regulator 1.05V output, connect to a 2.2µH or 4.7µH inductor.
4 GND power_in Ground.
5 MDI[0]+ bidirectional MDI pair 0 positive: BI_DA+/- in MDI mode (first pair in 1000Base-T) and transmit pair in 10/100 MDI mode, acting as BI_DB+/- receive pair in MDI crossover mode.
6 MDI[0]- bidirectional MDI pair 0 negative: BI_DA+/- in MDI mode (first pair in 1000Base-T) and transmit pair in 10/100 MDI mode, acting as BI_DB+/- receive pair in MDI crossover mode.
7 AVDD10 power_in Analog 1.05V power supply; also the feedback pin for the switching regulator.
8 MDI[1]+ bidirectional MDI pair 1 positive: BI_DB+/- in MDI mode and receive pair in 10/100 MDI mode, acting as BI_DA+/- transmit pair in MDI crossover mode.
9 MDI[1]- bidirectional MDI pair 1 negative: BI_DB+/- in MDI mode and receive pair in 10/100 MDI mode, acting as BI_DA+/- transmit pair in MDI crossover mode.
10 AVDD33 power_in Analog 3.3V power supply.
11 MDI[2]+ bidirectional MDI pair 2 positive: BI_DC+/- in MDI mode and BI_DD+/- in MDI crossover mode.
12 MDI[2]- bidirectional MDI pair 2 negative: BI_DC+/- in MDI mode and BI_DD+/- in MDI crossover mode.
13 AVDD10 power_in Analog 1.05V power supply.
14 MDI[3]+ bidirectional MDI pair 3 positive: BI_DD+/- in MDI mode and BI_DC+/- in MDI crossover mode.
15 MDI[3]- bidirectional MDI pair 3 negative: BI_DD+/- in MDI mode and BI_DC+/- in MDI crossover mode.
16 NC unconnected Not connected.
17 NC unconnected Not connected.
18 RXDV/PHY_AD2 output Receive data valid to the MAC in RGMII/GMII mode; sampled at power-up/reset as PHY address bit 2, which must be pulled high or low through a resistor (e.g., 4.7kΩ).
19 RXD0 output Receive data bit 0 from PHY to MAC (RXD[3:0] in RGMII, RXD[7:0] in GMII), latched at power-up/reset.
20 DVDD33 power_in Digital I/O power supply, 3.3V or 2.5V for RGMII/GMII I/O on RTL8211EG-VB.
21 RXD1 output Receive data bit 1 from PHY to MAC, latched at power-up/reset.
22 RXD2 output Receive data bit 2 from PHY to MAC, latched at power-up/reset.
23 RXD3 output Receive data bit 3 from PHY to MAC, latched at power-up/reset.
24 RXC output Continuous receive reference clock of 125MHz, 25MHz or 2.5MHz, derived from the received data stream.
25 RXD4/SELRGV output Receive data bit 4 in GMII mode; sampled at reset as SELRGV, pull up for 3.3V RGMII/GMII and pull down for 2.5V RGMII/GMII.
26 DVDD33 power_in Digital I/O power supply, 3.3V or 2.5V for RGMII/GMII I/O on RTL8211EG-VB.
27 RXD5/TXDLY output Receive data bit 5 in GMII mode; sampled at reset as RGMII transmit clock timing control (1 adds 2ns delay to TXC for TXD latching).
28 RXD6/RXDLY output Receive data bit 6 in GMII mode; sampled at reset as RGMII receive clock timing control (1 adds 2ns delay to RXC for RXD latching).
29 RXD7/AN0 output Receive data bit 7 in GMII mode; sampled at reset as auto-negotiation configuration bit AN[0].
30 RXER/AN1 output Receive error in GMII mode; sampled at reset as auto-negotiation configuration bit AN[1].
31 COL/Mode output Collision indication in half-duplex GMII mode; sampled at reset as RGMII/GMII mode select (pull up for RGMII, pull down for GMII).
32 CRS output Carrier sense output.
33 DVDD10 power_in Digital power supply, 1.05V.
34 GTX_CLK input Transmit reference clock input from MAC, 125MHz in GMII and RGMII modes.
35 TXEN input Transmit enable from MAC (GMII), and transmit control signal from MAC in RGMII mode.
36 TXD0 input Transmit data bit 0 from MAC; internal pull-down during power-on reset.
37 DVDD33 power_in Digital I/O power supply, 3.3V or 2.5V for RGMII/GMII I/O on RTL8211EG-VB.
38 PHYRSTB input Hardware reset, active low; must be asserted low for at least 10ms for a complete PHY reset, which clears all registers.
39 TXD1 input Transmit data bit 1 from MAC; internal pull-down during power-on reset.
40 TXD2 input Transmit data bit 2 from MAC; internal pull-down during power-on reset.
41 TXD3 input Transmit data bit 3 from MAC; internal pull-up during power-on reset.
42 TXCLK output GMII transmit reference clock output, 25MHz or 2.5MHz depending on speed.
43 TXD4 input GMII transmit data bit 4 from MAC.
44 TXD5 input GMII transmit data bit 5 from MAC.
45 TXD6 input GMII transmit data bit 6 from MAC.
46 TXD7 input GMII transmit data bit 7 from MAC.
47 TXER input Transmit error from MAC; connect to GND if the MAC has no TXER pin.
48 DVDD10 power_in Digital power supply, 1.05V.
49 DVDD33 power_in Digital power supply, 3.3V.
50 PHY_AD0/LED0 output PHY address bit 0 sampled at power-up/reset (pull-up through resistor), also LED0 output which blinks while transmitting or receiving.
51 PHY_AD1/LED1 output PHY address bit 1 sampled at power-up/reset (pull-down through resistor), also LED1 output which is low for link up and high for link down at any speed.
52 LED2 output LED2 output with no default setting, configurable through the extension page LED registers.
53 MDC input Management data clock input for the MDC/MDIO management interface (internal pull-up).
54 MDIO bidirectional Management data input/output, pulled up to 3.3V or 2.5V matching the RGMII/GMII signaling voltage.
55 PMEB output Open-drain power management event output, set low on receipt of a magic packet or wake-up frame; supports 3.3V and 5V pull-up and may be left floating if unused.
56 INTB output Open-drain interrupt output, set low on a status change (active low); may be left floating if unused.
57 ENSWREG input Switching regulator enable: 3.3V enables the regulator and 0V disables it.
58 RSET output External resistor reference pin.
59 AVDD10 power_in Analog power supply, 1.05V.
60 AVDD33 power_in Analog power supply, 3.3V.
61 CKXTAL1 input 25/50MHz crystal input; connect to the oscillator output if an external 25/50MHz oscillator is used.
62 CKXTAL2 output 25/50MHz crystal output; connect to GND if an external 25/50MHz oscillator drives CKXTAL1.
63 GND power_in Ground.
64 VDDREG power_in Analog 3.3V power supply for the switching regulator.
65 GND passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Realtek Semicon
Package QFN-64-EP(9x9)
Category Interface
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage DVDD33, AVDD33 (3.3V) VDD33 -0.4 3.7 V 65
Supply voltage AVDD10, DVDD10 (1.05V) AVDD10, DVDD10 -0.1 1.26 V 65
2.5V RGMII/GMII supply voltage -0.2 2.8 V 65
Storage temperature -55 125 °C 65
Supply voltage DVDD33, AVDD33 2.97 3.3 3.63 V 65
Supply voltage AVDD10, DVDD10 0.95 1.05 1.09 V 65
2.5V RGMII/GMII supply voltage VDD 2.4 2.5 2.62 V 65
Ambient operating temperature TA 0 70 °C 65
Maximum junction temperature 125 °C 65
3.3V supply voltage (DC table) VDD33 2.97 3.3 3.63 V 67
2.5V RGMII/GMII supply voltage (DC table) 2.37 2.5 2.62 V 67
1.05V supply voltage (DC table) DVDD10, AVDD10 0.95 1.05 1.09 V 67
Minimum high level input voltage (3.3V) Vih (3.3V) 1.8 V 67
Maximum low level input voltage (3.3V) Vil (3.3V) 0.9 V 67
Minimum high level input voltage (2.5V) Vih (2.5V) 1.7 V 67
Maximum low level input voltage (2.5V) Vil (2.5V) 0.7 V 67
Input current Iin 0 0.5 µA Vin=VDD33 or GND 67
Parallel resonant crystal reference frequency Fref 25 MHz Parallel resonant, fundamental mode, AT-cut 66
Parallel resonant crystal frequency stability Fref Stability -30 30 ppm Ta=0°C~70°C 66
Parallel resonant crystal frequency tolerance Fref Tolerance -50 50 ppm Ta=25°C 66
Reference clock input duty cycle (crystal) Fref Duty Cycle 40 60 % 66
Equivalent series resistance ESR 30 Ω 66
Drive level DL 0.5 mW 66
Broadband peak-to-peak jitter (crystal) Jitter 200 ps 66
Oscillator frequency stability -30 30 ppm Ta = 0°C~70°C 66
Oscillator frequency tolerance -50 50 ppm Ta = 25°C 66
Oscillator duty cycle 40 60 % 66
Oscillator broadband peak-to-peak jitter 200 ps 66
Oscillator Vpeak-to-peak 3.15 3.3 3.45 V 66
Oscillator rise time (10%~90%) 10 ns 66
Oscillator fall time (10%~90%) 10 ns 66
Oscillator operating temperature range 0 70 °C 66
MDC high pulse width t1 160 ns 68
MDC low pulse width t2 160 ns 68
MDC period t3 400 ns 68
MDIO setup to MDC rising edge t4 10 ns 68
MDIO hold time from MDC rising edge t5 10 ns 68
MDIO valid from MDC rising edge t6 0 300 ns 68
TXCLK duty cycle t1, t2 40 50 60 % 100Mbps 69
TXEN, TXD[0:3] hold after TXCLK rising edge t4 0 25 ns 100Mbps 69
3.3V rise time Rt1 100 ms 64
2.5/1.8/1.5V RGMII rise time Rt1 100 ms 2.5V RGMII row only applies to this part 64
3.3V off time Rt2 100 ms 64
Core logic ready time Rt3 20 ms 64

CAD (KiCad official)

  • Symbol: RTL8211EG-VB-CG
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: rtl8211eg-vb-cg-etched.step / rtl8211eg-vb-cg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rtl8211eg-vb-cg.step / rtl8211eg-vb-cg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Realtek Semicon datasheet (79 pp, sha256 b081006e6619ba24, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF