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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

RTL8201CP-VD-LF

Realtek Semicon · Ethernet Transceivers · LQFP-48(7x7)

RTL8201CP-VD-LF from Realtek Semicon, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	COL	bidirectional	Collision Detect; LI/O latched during power-up/reset to configure LED mode; asserts high when collision detected on media through transformer.
2	TXEN	input	Transmit Enable; input indicates presence of valid nibble data on TXD[3:0] to PHY for transmission.
3	TXD3	input	Transmit Data[3]; MAC sources 4-bit nibble data synchronous with TXC when TXEN asserted.
4	TXD2	input	Transmit Data[2]; MAC sources 4-bit nibble data synchronous with TXC when TXEN asserted.
5	TXD1	input	Transmit Data[1]; MAC sources 4-bit nibble data synchronous with TXC when TXEN asserted.
6	TXD0	input	Transmit Data[0]; MAC sources 4-bit nibble data synchronous with TXC when TXEN asserted.
7	TXC	output	Transmit Clock; provides continuous clock as timing reference for TXD[3:0] and TXEN at 25MHz (100Mbps) or 2.5MHz (10Mbps).
8	PWFBIN	input	Power Feedback Input; receives 1.8V output from PWFBOUT through ferrite bead as part of internal voltage conversion circuit.
9	LED0/PHYAD0	bidirectional	PHY Address[0] / Link LED; LI/O latched during power-up/reset to configure PHY address; after reset drives Link LED status output.
10	LED1/PHYAD1	bidirectional	PHY Address[1] / Full Duplex LED; LI/O latched during power-up/reset to configure PHY address; after reset drives Full Duplex LED status output.
11	DGND	power_in	Digital Ground; should be connected to larger GND plane for optimal performance.
12	LED2/PHYAD2	bidirectional	PHY Address[2] / Activity LED; LI/O latched during power-up/reset to configure PHY address; CP mode: 10-Activity LED blinking on transmit/receive; BL mode: Link 10/Activity.
13	LED3/PHYAD3	bidirectional	PHY Address[3] / Activity LED; LI/O latched during power-up/reset to configure PHY address; CP mode: 100-Activity LED blinking on transmit/receive; BL mode: Link 100/Activity.
14	DVDD33	power_in	3.3V Digital Power Input; 3.3V power supply for digital circuit.
15	LED4/PHYAD4	bidirectional	PHY Address[4] / Collision LED; LI/O latched during power-up/reset to configure PHY address; after reset drives Collision LED that blinks when collisions occur.
16	RXC	output	Receive Clock; provides continuous clock reference for RXDV and RXD[0..3] signals at 25MHz (100Mbps) or 2.5MHz (10Mbps).
17	DGND	power_in	Digital Ground; should be connected to larger GND plane for optimal performance.
18	RXD3	output	Receive Data[3]; 4-bit parallel receive data aligned on nibble boundaries driven synchronously to RXC for external MAC unit.
19	RXD2	output	Receive Data[2]; 4-bit parallel receive data aligned on nibble boundaries driven synchronously to RXC for external MAC unit.
20	RXD1	output	Receive Data[1]; 4-bit parallel receive data aligned on nibble boundaries driven synchronously to RXC for external MAC unit.
21	RXD0	output	Receive Data[0]; 4-bit parallel receive data aligned on nibble boundaries driven synchronously to RXC for external MAC unit.
22	RXDV	output	Receive Data Valid; asserts high when received data present on RXD[3:0]; de-asserts at packet end; valid on rising edge of RXC.
23	CRS	bidirectional	Carrier Sense; LI/O latched during power-up/reset for mode configuration; asserts high when media not in Idle state.
24	RXER/FXEN	bidirectional	Receive Error / Fiber/UTP Enable; LI/O latched during power-up/reset to select media mode (1=Fiber mode, 0=UTP mode); after power-on operates as Receive Error output.
25	MDC	input	Management Data Clock; provides clock synchronous to MDIO for serial management interface; may be asynchronous to TXC/RXC; up to 2.5MHz maximum.
26	MDIO	bidirectional	Management Data Input/Output; bi-directional signal used to transfer management information via MDC/MDIO serial interface.
27	NC	unconnected	Not Connected; no connection required or permitted.
28	RTSET	input	Transmit Bias Resistor Connection; must be pulled to GND by 2KΩ (1%) resistor to define driving current for transmit DAC.
29	AGND	power_in	Analog Ground; should be connected to larger GND plane for optimal performance.
30	TPRX-	input	Receive Input (Negative); differential receive input pair shared by 100Base-TX, 100Base-FX and 10Base-T modes; connection through transformer.
31	TPRX+	input	Receive Input (Positive); differential receive input pair shared by 100Base-TX, 100Base-FX and 10Base-T modes; connection through transformer.
32	PWFBOUT	output	Power Feedback Output; 1.8V output from internal voltage regulator; requires 22µF tantalum and 0.1µF capacitor for compensation/de-coupling; connected to PWFBIN through ferrite bead.
33	TPTX-	output	Transmit Output (Negative); differential transmit output pair; MLT-3 encoded (100Base-TX), pseudo-ECL level (100Base-FX), or Manchester encoded (10Base-T).
34	TPTX+	output	Transmit Output (Positive); differential transmit output pair; MLT-3 encoded (100Base-TX), pseudo-ECL level (100Base-FX), or Manchester encoded (10Base-T).
35	AGND	power_in	Analog Ground; should be connected to larger GND plane for optimal performance.
36	AVDD33	power_in	3.3V Analog Power Input; 3.3V power supply for analog circuit; should be well decoupled.
37	ANE	input	Auto-Negotiation Enable; LI latched during power-up/reset; pull high (default) to enable auto-negotiation, low to disable and activate parallel detection.
38	DUPLEX	input	Duplex Mode; LI latched during power-up/reset; pull high for full duplex mode, low for half duplex mode; can be directly connected to GND or VCC.
39	SPEED	input	Speed Mode; LI latched during power-up/reset; pull high for 100Mbps operation, low for 10Mbps operation; can be directly connected to GND or VCC.
40	RPTR	input	Repeater Mode; pull high to enable repeater mode (default low for NIC/Switch mode); can be directly connected to GND or VCC.
41	LDPS	input	Link Down Power Saving; pull high to enable LDPS mode for 60-80% power reduction when link down (default low); can be directly connected to GND or VCC.
42	RESETB	input	Reset; pull low to reset chip; must be asserted low for minimum 10ms for complete reset; pull high for normal operation.
43	ISOLATE	input	Isolation; set high to isolate RTL8201CP from MAC and MDC/MDIO interface for minimum power consumption; can be directly connected to GND or VCC.
44	MII/SNIB	input	MII/SNI Mode Select; LI latched during power-up/reset; pull high (default) for MII mode, low for SNI mode (10Mbps only); can be directly connected to GND or VCC.
45	DGND	power_in	Digital Ground; should be connected to larger GND plane for optimal performance.
46	X1	input	25MHz Crystal Input; accepts 25MHz crystal input or external 25MHz oscillator output; drives internal PLL.
47	X2	output	25MHz Crystal Output; provides 25MHz crystal output; leave open when external 25MHz oscillator drives X1.
48	DVDD33	power_in	3.3V Digital Power Input; 3.3V power supply for digital circuit.

Key specifications

Parameter	Value
Manufacturer	Realtek Semicon
Package	LQFP-48(7x7)
Category	Interface
Pins	48

CAD (KiCad official)

Symbol: RTL8201CP-VD-LF
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: rtl8201cp-vd-lf-etched.step / rtl8201cp-vd-lf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rtl8201cp-vd-lf.step / rtl8201cp-vd-lf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Realtek Semicon datasheet (38 pp, sha256 fe7b3b45b8e89e51, retrieved 2026-09-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF