# RT9992ZQW

**Richtek Tech** · DC-DC Converters · WQFN-32-EP(4x4)

RT9992ZQW from Richtek Tech, in a WQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB1 | input | Feedback input pin of CH1; high impedance in shutdown. |
| 2 | PGOOD | output | Power good indicator output pin (open drain) that monitors the FB2, FB3 and FB4 voltage status. |
| 3 | FB5 | input | Feedback input pin of CH5 that selects the internal 2.5V feedback network if VFB5 is above 0.8V before CH5 is enabled, and is high impedance in shutdown. |
| 4 | VOUT5 | power_out | Output pin of CH5 (generic LDO); high impedance in shutdown. |
| 5 | PVDD5 | power_in | Power input pin of CH5, with an input voltage range of 2.7V to 5.5V. |
| 6 | EN5 | input | Enable pin of CH5. |
| 7 | SEQ | input | SEQ high selects the preset power on/off sequence, SEQ low enables CH1 to CH5 independently, and the logic state must not change during operation. |
| 8 | LX2 | output | Switch node of CH2; high impedance in shutdown. |
| 9 | PVDD2 | bidirectional | Power input pin of CH2 in step-down mode, or power output pin of CH2 in step-up mode. |
| 10 | VIN2 | power_in | Power input node of CH2 in step-up mode, connected to the power input node in front of the CH2 inductor. |
| 11 | EN2 | input | Enable pin of CH2 or enable pin of the preset on/off sequence. |
| 12 | FB2 | input | Feedback input pin of CH2; high impedance in shutdown. |
| 13 | SEL | input | Selects CH2 step-down mode (SEL high, connect to VBAT) or step-up mode (SEL low, connect to GND); the logic state must not change during operation. |
| 14 | PVDD4 | power_in | Power input pin of CH4. |
| 15 | LX4 | output | Switch node of CH4; high impedance in shutdown. |
| 16 | EN4 | input | Enable pin of CH4 or selects which preset on/off sequence is used. |
| 17 | FB4 | input | Feedback input pin of CH4; high impedance in shutdown. |
| 18 | FB3 | input | Feedback input pin of CH3; high impedance in shutdown. |
| 19 | EN3 | input | Enable pin of CH3 or selects which preset on/off sequence is used. |
| 20 | LX3 | output | Switch node of CH3; high impedance in shutdown. |
| 21 | PVDD3 | power_in | Power input pin of CH3. |
| 22 | EN6 | input | Enable pin of CH6 and PWM dimming input; holding EN6 low for more than 32.7ms turns off CH6. |
| 23 | LX6 | output | Switch node of CH6 in step-up mode; high impedance in shutdown. |
| 24 | VOUT6 | input | Sense pin for the CH6 output voltage in step-up mode and CH6 mode selection pin (below 0.3V selects current source mode, above 0.7V selects asynchronous step-up mode). |
| 25 | FB6 | input | Feedback input pin of CH6 in step-up mode, or current sink pin of CH6 in current source mode. |
| 26 | VDDM | power_in | Internal control circuit power pin, operating from 2.7V to 5.5V, that must connect to a bypass capacitor for better noise rejection. |
| 27 | PVDD6 | power_in | Power input pin of the CH6 NMOS driver; it connects to the output of the first enabled low-voltage synchronous step-up channel to bootstrap VDDM. |
| 28 | RTCPWR | power_out | RTC LDO output pin, regulated to 3.1V typical (3.0V to 3.2V at IOUT = 0mA); a 0.1µF capacitor is recommended for stability. |
| 29 | BAT | power_in | Battery power input pin and CH1 step-up power input node. |
| 30 | PVDD1 | power_out | Power output pin of CH1. |
| 31 | LX1 | output | Switch node of CH1; high impedance in shutdown. |
| 32 | EN1 | input | Enable pin of CH1. |
| 33 | GND | power_in | Ground exposed pad; it must be soldered to a large PCB and connected to GND for maximum power dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | WQFN-32-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage VDDM | VDDM | 2.7 |  | 5.5 | V |  | 7 |
| Junction Temperature Range |  | -40 |  | 125 | °C |  | 7 |
| Ambient Temperature Range |  | -40 |  | 85 | °C |  | 7 |
| Supply Voltage, VDDM |  | -0.3 |  | 7 | V |  | 7 |
| LX1, LX2, LX3, LX4 |  | -0.3 |  | 7 | V |  | 7 |
| LX1, LX2, LX3, LX4 |  | -0.3 |  | 10 | V | < 20ns | 7 |
| LX6, VOUT6 |  | -0.3 |  | 21 | V |  | 7 |
| LX6, VOUT6 |  | -8 |  | 24 | V | < 20ns | 7 |
| Other Pins |  | -0.3 |  | 7 | V |  | 7 |
| Power Dissipation WQFN-32L 4x4 | PD |  |  | 1.923 | W | TA = 25°C | 7 |
| Junction Temperature |  |  |  | 150 | °C |  | 7 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 7 |
| ESD Susceptibility HBM (Human Body Mode) |  |  |  | 2 | kV |  | 7 |
| ESD Susceptibility MM (Machine Mode) |  |  |  | 200 | V |  | 7 |
| Package Thermal Resistance, junction to ambient | θJA |  |  | 52 | °C/W | WQFN-32L 4x4 | 7 |
| Package Thermal Resistance, junction to case | θJC |  |  | 7 | °C/W | WQFN-32L 4x4 | 7 |
| VDDM Startup Voltage | VST | 1.5 |  |  | V | For Bootstrap, First Rising | 7 |
| Shutdown Supply Current into BAT (including RTC LDO quiescent current) |  |  | 7 | 20 | μA | VBAT = 4.2V, VPVDD6 = 3V | 7 |
| Shutdown Supply Current into PVDD6 |  |  |  | 1 | μA | VBAT = 4.2V, VPVDD6 < VBAT | 7 |
| Shutdown Supply Current into VDDM | IOFF |  | 1 | 10 | μA | ENx = 0, VSEQ = 0V, SEL = 0V | 7 |
| CH1 (Synchronous Step-Up) Supply Current into VDDM | IQ1 |  |  | 800 | μA | Non Switching, VEN1 = 3.3V, VFB1 = 0.9V, VSEQ= 0V | 7 |
| CH6 (WLED) in Current Source Mode Supply Current into VDDM | IQ6c |  |  | 600 | μΑ | VEN6 = 3.3V, VOUT6 = 0V | 8 |
| CH1, 2, 3, 4 Operation Frequency | fOSC | 1800 | 2000 | 2200 | kHz |  | 8 |
| CH6 Operation Frequency | fOSC6 | 900 | 1000 | 1100 | kHz |  | 8 |
| CH1 Maximum Duty Cycle (Step-Up) |  | 80 | 83.5 | 87 | % | VFB1 = 0.7V | 8 |
| CH2 Maximum Duty Cycle (Step-Up) |  | 80 | 83.5 | 87 | % | VFB2 = 0.7V | 8 |
| CH6 Maximum Duty Cycle (Step-Up) |  | 91 | 93 | 97 | % | VFB6 = 0.15V, VOUT6 = 1V | 8 |
| Feedback Regulation Voltage @ FB1, FB2, FB3, and FB4 |  | 0.788 | 0.8 | 0.812 | V |  | 8 |
| Sink Current into FB6 (CS mode) |  | 28.5 | 30 | 31.5 | mA | VOUT6 = 0V, Current Source | 8 |
| Dropout Voltage @ FB6 (CS mode) |  |  |  | 0.6 | V | VOUT6 = 0V, VDDM = 3.3V, Current Source | 8 |
| Feedback Regulation Voltage @ FB6 | VFB6 | 0.237 | 0.25 | 0.263 | V | VOUT6 = 1V. Step-Up | 8 |
| CH1 On Resistance of P-MOSFET | RDS(ON) |  | 200 | 300 | mΩ | P-MOSFET, VPVDD1 = 3.3V | 8 |
| CH1 On Resistance of N-MOSFET | RDS(ON) |  | 130 | 250 | mΩ | N-MOSFET, VPVDD1 = 3.3V | 8 |
| CH1 Current Limitation (Step-Up) | ILIM1 | 2.2 | 3 | 4 | A |  | 8 |
| CH2 On Resistance of P-MOSFET | RDS(ON) |  | 400 | 550 | mΩ | P-MOSFET, VPVDD2 = 3.3V | 8 |
| CH2 On Resistance of N-MOSFET | RDS(ON) |  | 260 | 400 | mΩ | N-MOSFET, VPVDD2 = 3.3V | 8 |
| CH2 Current Limitation (Step-Down) | ILIM2_D | 1 | 1.5 | 2 | A |  | 8 |
| CH2 Current Limitation (Step-Up) | ILIM2_U | 1.5 | 2.1 | 3 | A |  | 8 |
| CH3 Current Limitation (Step-Down) | ILIM3 | 1 | 1.5 | 2 | A |  | 8 |
| CH4 Current Limitation (Step-Down) | ILIM4 | 1.5 | 2 | 2.4 | A |  | 8 |
| CH6 On Resistance of N-MOSFET | RDS(ON) |  | 0.75 | 1.1 | Ω | N-MOSFET | 8 |
| CH6 Current Limitation | ILIM6 | 0.6 | 0.8 | 1 | A | N-MOSFET | 8 |
| Over Voltage Protection PVDD1, PVDD2 (CH2 in Step-Up) |  | 5.9 | 6.15 | 6.4 | V |  | 9 |
| Over Voltage Protection @ VOUT6 | VOVP6 | 17 | 19 | 21 | V | Step-Up | 9 |
| VDDM Over Voltage Protection |  | 5.9 | 6.15 | 6.4 | V |  | 9 |
| VDDM UVLO Threshold, VDDM Rising |  | 2.4 |  | 2.7 | V |  | 9 |
| VDDM UVLO Threshold, VDDM Falling |  | 1.7 | 2.1 | 2.4 | V |  | 9 |
| BAT UVLO Threshold, BAT Rising |  | 1.3 | 1.4 | 1.5 | V |  | 9 |
| BAT UVLO Threshold, BAT Falling |  | 1.2 | 1.3 | 1.4 | V |  | 9 |
| Thermal Shutdown | TSD | 125 | 160 |  | °C |  | 9 |
| EN1 to 6, SEL, SEQ Threshold Voltage Logic-High | VIH | 1.3 |  |  | V |  | 9 |
| EN1 to 6, SEL, SEQ Threshold Voltage Logic-Low | VIL |  |  | 0.4 | V |  | 9 |
| CH5 LDO Input Voltage Range (PVDD5) | VPVDD5 | 2.7 |  | 5.5 | V |  | 9 |
| CH5 LDO Output Voltage Range | VOUT5 | 1.5 |  | 3.3 | V | By external feedback | 9 |
| CH5 Feedback Regulation Voltage @ FB5 | VFB5 | 0.493 | 0.5 | 0.507 | V | Using external feedback loop | 9 |
| CH5 Regulated Output Voltage @ VOUT5 | VREG5 | 2.45 | 2.5 | 2.55 | V | Using internal feedback loop | 9 |
| CH5 Max Current Limit | ILIM5 | 200 | 300 | 400 | mA | VPVDD5 = 3.3V | 9 |
| RTC LDO Input Voltage Range | VDDI |  |  | 5.5 | V | Max of BAT and PVDD6 | 10 |
| RTC LDO Regulated Output Voltage @ RTCPWR |  | 3 | 3.1 | 3.2 | V | IOUT = 0mA | 10 |
| RTC LDO Quiescent Current | IQ |  | 5 | 8 | μA | VDDI = 4.2V | 10 |

## CAD (KiCad official)

- Symbol: `RT9992ZQW`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm`
- 3D model: WQFN-32-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `rt9992zqw-etched.step` / `rt9992zqw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt9992zqw.step` / `rt9992zqw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Richtek Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586184447221764096) (19 pp, sha256 `930f7fc76cf0aef0`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/rt9992zqw-datasheet.pdf)