component
RT9742EGJ5
Public Made by Adomby adom
Richtek Tech Power Distribution Switches, TSOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownRT9742EGJ5
Richtek Tech · Power Distribution Switches · TSOT-23-5
RT9742EGJ5 from Richtek Tech, in a TSOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Switch output voltage, the source of the internal N-MOSFET, which supplies the load. |
| 2 | GND | power_in | Ground. |
| 3 | FLG | output | Active-low N-channel open-drain fault flag output that asserts after about 10 ms of over-current or over-temperature, and needs an external pull-up resistor (10k to 100k). |
| 4 | EN/EN | input | Chip enable input (active high or active low depending on version), with VIH 1.5V min and VIL 0.75V max, 0V to 6V range; do not float it. |
| 5 | VIN | power_in | Power input voltage and drain of the internal MOSFET, with a 2.7V to 6V operating range and 7V absolute maximum; bypass with a 10µF capacitor to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | TSOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Input Voltage, VIN | VIN | 2.7 | 6 | V | 5 | ||
| EN Voltage | EN | 0 | 6 | V | 5 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 5 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 5 | ||
| Supply Input Voltage, VIN | VIN | 7 | V | 5 | |||
| EN Voltage | EN | -0.3 | 7 | V | 5 | ||
| FLAG Voltage | FLG | 7 | V | 5 | |||
| Power Dissipation, PD (TSOT-23-5) | PD | 0.49 | W | TA = 25°C | 5 | ||
| Junction Temperature | TJ | 150 | °C | 5 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 5 | ||
| Lead Temperature (Soldering) | 260 | °C | Soldering, 10 sec. | 5 | |||
| ESD Susceptibility HBM | 2 | kV | Human Body Model | 5 | |||
| Package Thermal Resistance, θJA (TSOT-23-5) | θJA | 203 | °C/W | JEDEC 51-7 four-layer board, TA = 25°C | 5 | ||
| Input Quiescent Current | IQ | 30 | 40 | μA | Switch on, VOUT = open | 5 | |
| Input Shutdown Current | ISHDN | 0.1 | 1 | μA | VIN = 5V, no load on OUT, device OFF, VEN = 0V or VEN = 5V | 5 | |
| Switch On Resistance (RT9742XXJ5/V, this variant) | RDS(ON) | 70 | mΩ | 5 | |||
| Over Current Trip Threshold (RT9742E group) | ITRIP | 1.55 | 2.1 | 2.25 | A | VIN = 5V, 100A/s | 5 |
| Current Limit (RT9742E group) | ILIM | 1.5 | 1.65 | 1.8 | A | VOUT = 1V | 6 |
| EN/EN Threshold Logic_High Voltage | VIH | 1.5 | V | VIN = 2.7V to 6V | 6 | ||
| EN/EN Threshold Logic_Low Voltage | VIL | 0.75 | V | VIN = 2.7V to 6V | 6 | ||
| EN/EN Input Current | IEN | 0.5 | 0.5 | μA | VEN = 0V, VEN = 5V | 6 | |
| Output Leakage Current | ILEAKAGE | 0.5 | 1 | μA | VEN = 0V, RLOAD = 0 | 6 | |
| Reverse Leakage Current | IREV | 1 | μA | VOUT = 5V, VIN = 0V | 6 | ||
| Reverse Voltage Trip Point | VREV | 200 | mV | VOUT vs VIN (comparison symbol lost in extraction) | 6 | ||
| Output Turn-On Rise Time | tON_RISE | 1.5 | ms | 10% to 90% of VOUT rising | 6 | ||
| Turn-On Time | tON | 2.1 | ms | From enable to 90% of VOUT | 6 | ||
| FLG Output Resistance | RFLG | 10 | Ω | ISINK = 1mA | 6 | ||
| FLG Off Current | IFLG_OFF | 0.01 | 1 | μA | VFLG = 5V | 6 | |
| FLG Delay Time | tD | 10 | ms | From fault condition to FLG assertion | 6 | ||
| Shutdown Auto-Discharge Resistance | RDischarge | 100 | Ω | VEN = 0V, VEN = 5V | 6 | ||
| Under-Voltage Lockout | VUVLO | 2.4 | V | VIN rising | 6 | ||
| Under-Voltage Hysteresis | VUVLO | 0.1 | V | VIN decreasing | 6 | ||
| Thermal Shutdown Protection | TSD | 140 | °C | Note 6 (guaranteed by design) | 6 | ||
| Thermal Shutdown Hysteresis | TSD | 20 | °C | Note 6 (guaranteed by design) | 6 |
CAD (KiCad official)
- Symbol:
RT9742EGJ5 - Footprint:
Package_TO_SOT_SMD:TSOT-23-5 - 3D model: TSOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
rt9742egj5-etched.step/rt9742egj5-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt9742egj5.step/rt9742egj5.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (19 pp, sha256
4512463eff0aa45d, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).