component
RT9718BGQW
Public Made by Adomby adom
Richtek Tech Monitors & Reset Circuits, DFN-8-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 16d ago |
| viewers | 16d ago |
| package.json | 16d ago |
| page.json | 16d ago |
| README.md | 16d ago |
| rt9718bgqw-etched.glb | 16d ago |
| rt9718bgqw-etched.step | 16d ago |
| rt9718bgqw-hero.glb | 16d ago |
| rt9718bgqw-hero.overlay.json | 16d ago |
| rt9718bgqw.glb | 16d ago |
| rt9718bgqw.kicad_mod | 16d ago |
| rt9718bgqw.kicad_sym | 16d ago |
| rt9718bgqw.lbr | 16d ago |
| rt9718bgqw.step | 16d ago |
RT9718BGQW
Richtek Tech · Monitors & Reset Circuits · DFN-8-EP(2x2)
RT9718BGQW from Richtek Tech, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | The input power source, which can withstand up to 30V input. |
| 2 | GND | power_in | Analog ground. |
| 3 | NC | unconnected | No internal connection. |
| 4 | WRN | output | Open-drain logic output that turns LOW when any protection event occurs. |
| 5 | EN | input | Active-low chip enable: pull low or leave floating to enable the IC, force high (>1.5V) to disable it. |
| 6 | VB | power_in | Battery voltage monitoring input, connected to the battery pack positive terminal via an isolation resistor. |
| 7 | ILIM | passive | Over current protection threshold setting pin; connect a resistor between this pin and GND to set the OCP threshold. |
| 8 | VOUT | power_out | Output through the power MOSFET. |
| 9 | GND | power_in | Exposed pad, must be soldered to a large PCB and connected to GND for maximum thermal dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | DFN-8-EP(2x2) |
| Category | Power Management ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operation Voltage (RT9718B) | VIN | 4 | 5.5 | V | Power On Reset, RT9718B | 3 | |
| Supply Voltage POR Threshold | VPOR | 2.5 | 2.7 | 2.9 | V | VPOR Rising | 3 |
| Deglitch Time of POR | 8 | ms | 3 | ||||
| Under Voltage Lockout Threshold | VUVLO | 2.45 | 2.75 | V | VUVLO Falling | 3 | |
| Input Quiescent Current | IQ | 500 | 600 | µA | EN = 0V | 3 | |
| Input Shutdown Current | ISHDN | 65 | 95 | µA | EN = 5V | 3 | |
| Input OVP Threshold Voltage (RT9718B) | VIN_OVP | 5.6 | 5.85 | 6 | V | RT9718B | 3 |
| Input OVP Hysteresis | 60 | 100 | mV | 3 | |||
| Input OVP Propagation Delay | 1 | µs | VOUT = VIN x 80% | 3 | |||
| Input OVP Recovery Delay | 8 | ms | 3 | ||||
| Over Current Protection | IOCP | 0.93 | 1 | 1.07 | A | RILIM = 25k | 4 |
| Battery OVP Threshold Rising | VBOVP | 4.3 | 4.35 | 4.4 | V | Threshold Rising | 4 |
| Battery OVP Falling Threshold | VBOVP | 4.225 | V | 4 | |||
| VB Pin Leakage Current | 20 | nA | VVB = 4.4V | 4 | |||
| EN Logic-High Threshold | VIH | 1.5 | V | 4 | |||
| EN Logic-Low Threshold | VIL | 0.4 | V | 4 | |||
| EN Internal Pull Down Resistor | 100 | 200 | 400 | kΩ | 4 | ||
| WRN Output Logic Low | 0.35 | 0.8 | V | Sink 5mA | 4 | ||
| WRN Output Logic High Leakage Current | 1 | µA | 4 | ||||
| On Resistance | RON | 200 | 300 | mΩ | IOUT = 500mA, 4.3V < VIN < 6.5V | 4 | |
| Over Current Protection Blanking Time | TOC | 180 | µs | 4 | |||
| Over Current Recover Delay | 64 | ms | 4 | ||||
| Battery OVP Hysteresis | 30 | mV | 4 | ||||
| Battery OVP Blanking Time | TVBOV | 180 | µs | 4 | |||
| Battery OVP Recover Delay | 8 | ms | 4 | ||||
| OTP Threshold Rising | 140 | °C | Rising | 4 | |||
| OTP Hysteresis | 20 | °C | Hysteresis | 4 | |||
| OTP Recover Delay | 8 | ms | 4 | ||||
| Soft-Start Time | TSD | 8 | ms | 4 | |||
| Junction Temperature Range | TJ | -40 | 125 | °C | 3 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 3 | ||
| Supply Input Voltage | VIN | -0.3 | 30 | V | 3 | ||
| VOUT, VB | -0.3 | 7 | V | 3 | |||
| Other Pins | -0.3 | 6 | V | 3 | |||
| Power Dissipation | PD | 0.606 | W | TA = 25°C, WDFN-8L 2x2 | 3 | ||
| Junction Temperature | TJ | 150 | °C | 3 | |||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 3 | |||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| ESD Susceptibility HBM | 2 | kV | Human Body Mode | 3 | |||
| ESD Susceptibility MM | 200 | V | Machine Mode | 3 | |||
| Package Thermal Resistance, Junction to Ambient | θJA | 165 | °C/W | WDFN-8L 2x2 | 3 | ||
| Package Thermal Resistance, Junction to Case | θJC | 20 | °C/W | WDFN-8L 2x2 | 3 |
CAD (KiCad official)
- Symbol:
RT9718BGQW - Footprint:
Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm - 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
rt9718bgqw-etched.step/rt9718bgqw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt9718bgqw.step/rt9718bgqw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (10 pp, sha256
34899e92895406a2, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).