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RT9471DGQW

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Richtek Tech Battery Management, WQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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RT9471DGQW

Richtek Tech · Battery Management · WQFN-24(4x4)

RT9471DGQW from Richtek Tech, in a WQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBUS power_in Charger input voltage; the internal reverse block MOSFET (Q1) is connected between VBUS and PMID with VBUS on source, and a capacitor from VBUS to GND must be placed as close as possible to the IC.
2 D+ bidirectional Positive line of the USB data pair used for D+/D- based USB host/charging port detection, including data contact detection and primary and secondary detection in BC1.2.
3 D- bidirectional Negative line of the USB data pair used for D+/D- based USB host/charging port detection, including data contact detection and primary and secondary detection in BC1.2.
4 STAT output Open-drain charger status output that indicates charger status and must be connected to a logic rail via a 2.2k to 10k resistor.
5 SCL input I2C interface clock input that must be connected to the logic rail through a 10k resistor.
6 SDA bidirectional I2C interface data pin that must be connected to the logic rail through a 10k resistor.
7 INT output Open-drain active-low interrupt output that sends low pulses to the host to report charger device status and faults, connected to a logic rail through a 10k resistor.
8 NC unconnected No internal connection.
9 CE input Charge enable input; when driven low, battery charging is enabled.
10 NC unconnected No internal connection.
11 TS input Temperature qualification voltage input for the JEITA profile that connects to an NTC thermistor, and charging suspends when the TS voltage is out of range.
12 QON input BATFET (Q4) enable control input with an internal pull-high to the bias circuit via a 250k resistor, where a logic low exits ship mode or triggers system reset when no VBUS is present.
13 BAT power_in Battery connection point to the positive terminal of the battery pack, with the internal current sensing resistor connected between SYS and BAT.
14 BAT power_in Battery connection point to the positive terminal of the battery pack, with the internal current sensing resistor connected between SYS and BAT.
15 SYS power_out Converter output connection point, with the internal current sensing resistor connected between SYS and BAT and capacitors placed close to the pin.
16 SYS power_out Converter output connection point, with the internal current sensing resistor connected between SYS and BAT and capacitors placed close to the pin.
17 GND power_in Power ground.
18 GND power_in Power ground.
19 SW passive Switching node connecting to the output inductor, internally tied to the high-side MOSFET source and low-side MOSFET drain, with a bootstrap capacitor connected from SW to BTST.
20 SW passive Switching node connecting to the output inductor, internally tied to the high-side MOSFET source and low-side MOSFET drain, with a bootstrap capacitor connected from SW to BTST.
21 BTST power_in PWM high-side driver positive supply connected to the cathode of the internal bootstrap diode, with the bootstrap capacitor connected from SW to BTST.
22 REGN power_out PWM low-side driver and internal supply output connected to the anode of the bootstrap diode, with a capacitor from REGN to GND placed close to the IC.
23 PMID power_in Connected to the drain of the reverse blocking MOSFET (Q1) and the drain of the high-side switching MOSFET (Q2), with a capacitor from PMID to GND.
24 VAC input Input voltage sensing pin that must be tied to VBUS.
25 Thermal Pad power_in Thermal pad and ground reference that must be connected to GND and well soldered to a large PCB copper area for maximum power dissipation.

Key specifications

Parameter Value
Manufacturer Richtek Tech
Package WQFN-24(4x4)
Category Power Management (PMIC)
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
IBAT Q4 disabled quiescent/discharge current (BAT) in Q4 Disabled IBAT_Q4_DIS 15 32 A VBAT = 4.5V, High-Z mode and I2C disabled, Q4 disabled 7
Battery Discharge Current (BAT) in Q4 Enable IBAT_Q4_EN 55 85 A VBAT = 4.5V, High-Z mode and I2C disabled, Q4 enabled 7
Input Supply Current (VBUS) in Buck Mode, High-Z IBUS_HIZ 50 86 A VBUS = 5V, High-Z mode and no battery 7
Input Supply Current (VBUS) in Buck Mode, High-Z IBUS_HIZ 52 88 A VBUS = 12V, High-Z mode and no battery 7
Input Supply Current (VBUS) in Buck Mode IBUS_BUCK 5 7 mA VBUS > VBUS_MIN_RISE, VBUS > VBAT, converter switching, VBAT = 3.8V, ISYS = 0A 7
Battery Discharge Current (BAT) in Boost Mode IBAT_BOOST 4 5 mA VBAT = 4.2V, boost mode, IBUS = 0A, converter switching 7
VBUS Operating Range VBUS_OP 3.9 13.5 V VBUS rising 7
REGN Turn Off Level with Only VBUS VBUS_UVLO 3 3.3 3.6 V VBUS falling 7
Sleep Mode Falling Threshold VSLEEP_FALL 10 60 120 mV VAC falling, VAC, VBAT 7
Sleep Mode Rising Threshold VSLEEP_RISE 160 250 340 mV VAC rising, VAC, VBAT 7
VAC 5.8V Over-Voltage rising threshold VAC_OVP_RISE 5.5 5.8 6.1 V VAC rising 7
VAC 6.5V Over-Voltage rising threshold VAC_OVP_RISE 6.2 6.5 6.8 V VAC rising 7
VAC 10.9V Over-Voltage Rising Threshold VAC_OVP_RISE 10.3 10.9 11.5 V VAC rising 7
VAC 14V Over-Voltage Rising Threshold VAC_OVP_RISE 13.3 14 14.7 V VAC rising 7
BAT for Active I2C, No Adapter VBAT_UVLO 2 2.2 2.4 V VBAT rising 7
Battery Depletion Falling Threshold VBAT_DPL_FALL 2.15 2.38 2.65 V VBAT falling 8
Battery Depletion Rising Threshold VBAT_DPL_RISE 2.4 2.6 2.8 V VBAT rising 8
Bad Adapter Detection Rising Threshold VBUS_MIN_RISE 3.6 3.8 4 V VBUS rising 8
System Regulation Voltage VSYS_MIN 3.5 V VBAT < VSYS_MIN = 3.5V, Q4 disabled/enable 8
Charge Voltage Range VBAT_REG_RANGE 3.9 4.7 V Default = 4.2V 8
Charge Voltage Setting Accuracy VBAT_REG_ACC -0.5 0.5 % 8
Charge Current Regulation Range ICHG_REG_RANGE 0 3150 mA Default = 2000mA 8
Charge Current Regulation Accuracy ICHG_REG_ACC -20 20 % VBAT=3.8V, ICHG_REG < 150mA 8
Charge Current Regulation Accuracy ICHG_REG_ACC -10 10 % VBAT=3.8V, 150mA ≤ ICHG_REG < 750mA 8
Charge Current Regulation Accuracy ICHG_REG_ACC -5 5 % VBAT=3.8V, ICHG_REG ≥ 750mA 8
Pre-Charge Falling Threshold VPRE_CHG_FALL 2.75 2.9 3.05 V ICHG = 200mA, VPRE_CHG = 3.1V 8
Pre-Charge Rising Threshold VPRE_CHG_RISE 2.95 3.1 3.25 V Pre-charge to fast charge, VPRE_CHG = 3.1V 8
OTG Voltage Limit Regulation Range VOTG_CV_RANGE 4.85 5.3 V Default = 5.15V 11
OTG Voltage Limit Regulation Accuracy VOTG_CV_ACC -3 3 % VBAT = 3.8V, IPMID = 0A, VOTG_REG = 5.15V 11
OTG Current Limit Regulation Accuracy IOTG_CC 1.2 1.4 1.6 A IOTG_LIMIT_REG_SEL = 1.2A 11
OTG Current Limit Regulation Accuracy IOTG_CC 0.5 0.6 0.7 A IOTG_LIMIT_REG_SEL = 0.5A 11
OTG Over-Voltage Threshold VOTG_OVP 6.2 6.5 6.8 V VAC rising, VAC_OVP = 6.5V 11
PWM Switching Frequency (buck) fSW_BUCK 1350 1500 1650 kHz Oscillator frequency, buck mode 11
PWM Switching Frequency (boost) fSW_BOOST 1350 1500 1650 kHz Oscillator frequency, boost mode 11
REGN LDO Output Voltage VREGN 4.5 4.9 5.3 V VBUS = 9V, IREGN = 40mA 11
REGN LDO Output Voltage VREGN 4.5 4.9 5 V VBUS = 5V, IREGN = 20mA 11
Input High Threshold Voltage (CE, PSEL, SCL, SDA) VIH_CTRL 1.3 V 11
Input Low Threshold Voltage (CE, PSEL, SCL, SDA) VIL_CTRL 0.4 V 11
High Level Leakage Current (CE, PSEL, SCL, SDA) IBIAS 1 A Pull high to 1.8V 11
Output Low Threshold Voltage (PG, STAT, INT) VOL_CTRL 0.4 V 11
Data Detect Voltage VDAT_REF 0.25 0.325 0.4 V 11
D- Current Sink ID-_ISNK 50 100 150 A 11
D+D- Leakage Current ID+D-_LKG -1 1 A 11
D- Pulldown for Connection Check RD-_19K 14.25 19.53 24.8 k 11
Charge Safe Timer tCHG_SAFE_TMR 9 10 11 hr Timer = 10hr 12
Back-Ground Charge Timer tBG_CHG_TMR 29 30 31 min Timer = 30min 12
QON Low Time to Exit Shipping Mode tSHIPMODE_EXIT 0.9 1.1 1.3 s 12
QON Low Time to Reset System tQON_RST 9 10 11 s 12
BATFET Reset Time tBATFET_RST 430 453 480 ms 12
Enter Shipping Mode Delay Time tSHIP_MODE_ENTER 11 12 13 s 12
SCL Clock fSCL 3.4 MHz CB ≤ 100pF 12
SCL Clock fSCL 1.7 MHz 100pF < CB ≤ 400pF 12
Supply Pin Voltage, VBUS (absolute maximum) VBUS -1.4 26 V 6
Terminal Pin Voltage, SW (absolute maximum) -0.3 16 V 6
Junction Temperature (absolute maximum) 150 C 6
Maximum Input Current, IBUS IBUS 3.2 A 6
Junction Temperature Range -40 125 C 6
Maximum Battery Voltage, VBAT VBAT 4.7 V 6
Package Thermal Resistance, WQFN-24L 4x4, junction-to-ambient JA 28 C/W WQFN-24L 4x4 6
Package Thermal Resistance, WQFN-24L 4x4, junction-to-case JC 7.1 C/W WQFN-24L 4x4 6

CAD (KiCad official)

  • Symbol: RT9471DGQW
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: WQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: rt9471dgqw-etched.step / rt9471dgqw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rt9471dgqw.step / rt9471dgqw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Richtek Tech datasheet (52 pp, sha256 0664f5347d4ed917, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF