component
RT9465GQW
Public Made by Adomby adom
Richtek Tech Battery Management, WQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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RT9465GQW
Richtek Tech · Battery Management · WQFN-16-EP(3x3)
RT9465GQW from Richtek Tech, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power input; bypass VIN to GND with a 2.2µF/25V ceramic capacitor. |
| 2 | VIN | power_in | Power input; bypass VIN to GND with a 2.2µF/25V ceramic capacitor (same net as pin 1). |
| 3 | REG | power_out | PWM low-side driver and bootstrap power supply; bypass REGN to GND with a 4.7µF/6.3V ceramic capacitor. |
| 4 | SDA | bidirectional | I2C interface serial data input/output, open-drain; an external 10kΩ pull-up resistor is required. |
| 5 | SCL | input | I2C interface serial clock input, open-drain; an external 10kΩ pull-up resistor is required. |
| 6 | EN | input | Device enable control; pull low to disable the device (EN high threshold is 1.2V minimum, low threshold 0.4V maximum). |
| 7 | INT | output | Open-drain interrupt signal to host; goes low when a fault occurs. |
| 8 | BAT- | input | Negative battery voltage sense input. |
| 9 | BAT+ | input | Positive battery voltage sense input. |
| 10 | AGND | power_in | Analog ground; connect to the exposed pad (pin 17) and AGND for maximum thermal dissipation. |
| 11 | PGND | power_in | Power ground. |
| 12 | PGND | power_in | Power ground (same net as pin 11). |
| 13 | SW | output | Switch node; connect to an external inductor (SW absolute maximum is −0.3V to 20V). |
| 14 | SW | output | Switch node; connect to an external inductor (same net as pin 13). |
| 15 | SW | output | Switch node; connect to an external inductor (same net as pin 13). |
| 16 | BOOT | power_out | Bootstrap supply for the high-side MOSFET; connect a 47nF/16V ceramic capacitor across BOOT and SW. |
| 17 | AGND | power_in | Exposed pad; analog ground that must be soldered to a large PCB and connected to AGND for maximum thermal dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | WQFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Quiescent current, no switching (VIN supply) | I(VIN)_no_SW | 2 | mA | PWM is non-switching, VIN = 5V, VBAT+ = 4.4V | 5 | ||
| Leakage current from battery | IBAT_leak | 1 | µA | Charger disable, VBAT = 3.8V | 5 | ||
| VIN under-voltage protection | VUVP | 3.67 | 3.8 | 3.93 | V | 5 | |
| VIN under-voltage protection hysteresis | VUVP_HYS | 120 | 200 | 280 | mV | 5 | |
| Input voltage regulation range (MIVR) | VMIVR | 3.9 | 13.4 | V | I2C programmable per 0.1V | 5 | |
| VMIVR accuracy | VMIVR_ACC | -3 | 3 | % | MIVR = 4.4V, 9V | 6 | |
| IC active threshold voltage (VIN UVLO) | VUVLO | 3.05 | 3.3 | 3.55 | V | VIN rising | 6 |
| VIN OVP threshold voltage | VINOVP | 13.5 | 14.5 | 15.5 | V | VIN rising | 6 |
| Battery OVP | VBATOVP | 102 | 104 | 106 | % | 6 | |
| Battery UVP | VBATUVP | 2.3 | 2.4 | 2.5 | V | VBAT falling | 6 |
| Battery voltage regulation (end of charge) | VOREG | 3.8 | 5.06 | V | I2C programmable per 20mV | 6 | |
| Battery voltage accuracy | VOREG_ACC | -1 | 1 | % | Temperature = 0 to 85°C | 6 | |
| Charging current | ICHG | 0.6 | 3 | A | I2C programmable per 0.1A | 6 | |
| ICHG accuracy | ICHG_ACC | -15 | 15 | % | VIN = 5V, charge current > 1A | 6 | |
| ICHG accuracy | ICHG_ACC | -10 | 10 | % | VIN = 9V, 12V, charge current > 1A | 6 | |
| ICHG accuracy | ICHG_ACC | -150 | 150 | mA | VIN = 5V, charge current < 1A | 6 | |
| ICHG accuracy | ICHG_ACC | -100 | 100 | mA | VIN = 9V, 12V, charge current < 1A | 6 | |
| End of charging current | IEOC | 0.6 | 1.6 | A | I2C programmable per 0.1A | 6 | |
| IEOC accuracy | IEOC_ACC | -15 | 15 | % | VIN = 5V, 9V, 12V, IEOC setting > 1A | 6 | |
| IEOC accuracy | IEOC_ACC | -150 | 150 | mA | VIN = 5V, 9V, 12V, IEOC setting < 1A | 6 | |
| High-side on-resistance | RON(Q1) | 17 | 21.5 | 26 | mΩ | From VIN to SW | 6 |
| Low-side on-resistance | RON(Q2) | 17 | 21.5 | 26 | mΩ | From SW to PGND | 6 |
| Switching frequency (1.5MHz) | fOSC1 | 1.35 | 1.5 | 1.65 | MHz | I2C programmable 1.5 MHz | 6 |
| Switching frequency (750kHz) | fOSC2 | 0.675 | 0.75 | 0.825 | MHz | I2C programmable 0.75MHz | 6 |
| Frequency accuracy | -10 | 10 | % | 7 | |||
| Minimum duty cycle | 0 | % | 7 | ||||
| VREG regulation | VREG | 4.74 | 4.9 | 5.06 | V | VIN = 5V | 7 |
| EN pull-low resistance | REN | 180 | 500 | 820 | kΩ | 7 | |
| I2C output low voltage | VOL | 0.4 | V | IDS = 10mA | 7 | ||
| SCL, SDA input logic high threshold voltage | VIH | 1.3 | V | 7 | |||
| SCL, SDA input logic low threshold voltage | VIL | 0.4 | V | 7 | |||
| SCL clock | 400 | kHz | 7 | ||||
| Load capacitance | CLOAD | 1 | pF | VPULL_UP = 1.8V | 7 | ||
| Junction temperature monitor accuracy | -3 | 3 | °C | 7 | |||
| EN input threshold voltage (high) | VIH | 1.2 | V | Logic high threshold | 7 | ||
| EN input threshold voltage (low) | VIL | 0.4 | V | Logic low threshold | 7 | ||
| Device turn-on delay time after EN pull-high | 500 | µs | After EN pull-High | 7 | |||
| Supply input voltage (recommended) | VIN | 3.9 | 14 | V | 5 | ||
| Charge current (recommended) | IBAT | 0.6 | 3 | A | 5 | ||
| Battery voltage (recommended) | VBAT | 3.8 | 5.06 | V | 5 | ||
| Junction temperature range (recommended) | -40 | 125 | °C | 5 | |||
| Ambient temperature range (recommended) | -40 | 85 | °C | 5 | |||
| Supply input voltage (absolute maximum) | VIN | -0.3 | 22 | V | 5 | ||
| BOOT (absolute maximum) | -0.3 | 22 | V | 5 | |||
| SW (absolute maximum) | -0.3 | 20 | V | 5 | |||
| REG, SCL, SDA, EN, INT, BAT+, BAT- (absolute maximum) | -0.3 | 6 | V | 5 | |||
| ESD susceptibility HBM | 2 | kV | 5 | ||||
| Lead temperature (soldering, 10 sec) | 260 | °C | 5 | ||||
| Junction temperature (absolute maximum) | 150 | °C | 5 | ||||
| Storage temperature range | -65 | 150 | °C | 5 | |||
| Power dissipation, WQFN-16L 3x3 | PD | 3.33 | W | TA = 25°C | 5 | ||
| Package thermal resistance, junction-to-ambient, WQFN-16L 3x3 | θJA | 30 | °C/W | 5 | |||
| Package thermal resistance, junction-to-case, WQFN-16L 3x3 | θJC | 7.5 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
RT9465GQW - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
rt9465gqw-etched.step/rt9465gqw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt9465gqw.step/rt9465gqw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (25 pp, sha256
e2a57a4fd80e8c64, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# RT9465GQW
**Richtek Tech** · Battery Management · WQFN-16-EP(3x3)
RT9465GQW from Richtek Tech, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power input; bypass VIN to GND with a 2.2µF/25V ceramic capacitor. |
| 2 | VIN | power_in | Power input; bypass VIN to GND with a 2.2µF/25V ceramic capacitor (same net as pin 1). |
| 3 | REG | power_out | PWM low-side driver and bootstrap power supply; bypass REGN to GND with a 4.7µF/6.3V ceramic capacitor. |
| 4 | SDA | bidirectional | I2C interface serial data input/output, open-drain; an external 10kΩ pull-up resistor is required. |
| 5 | SCL | input | I2C interface serial clock input, open-drain; an external 10kΩ pull-up resistor is required. |
| 6 | EN | input | Device enable control; pull low to disable the device (EN high threshold is 1.2V minimum, low threshold 0.4V maximum). |
| 7 | INT | output | Open-drain interrupt signal to host; goes low when a fault occurs. |
| 8 | BAT- | input | Negative battery voltage sense input. |
| 9 | BAT+ | input | Positive battery voltage sense input. |
| 10 | AGND | power_in | Analog ground; connect to the exposed pad (pin 17) and AGND for maximum thermal dissipation. |
| 11 | PGND | power_in | Power ground. |
| 12 | PGND | power_in | Power ground (same net as pin 11). |
| 13 | SW | output | Switch node; connect to an external inductor (SW absolute maximum is −0.3V to 20V). |
| 14 | SW | output | Switch node; connect to an external inductor (same net as pin 13). |
| 15 | SW | output | Switch node; connect to an external inductor (same net as pin 13). |
| 16 | BOOT | power_out | Bootstrap supply for the high-side MOSFET; connect a 47nF/16V ceramic capacitor across BOOT and SW. |
| 17 | AGND | power_in | Exposed pad; analog ground that must be soldered to a large PCB and connected to AGND for maximum thermal dissipation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | WQFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Quiescent current, no switching (VIN supply) | I(VIN)_no_SW | | | 2 | mA | PWM is non-switching, VIN = 5V, VBAT+ = 4.4V | 5 |
| Leakage current from battery | IBAT_leak | | | 1 | µA | Charger disable, VBAT = 3.8V | 5 |
| VIN under-voltage protection | VUVP | 3.67 | 3.8 | 3.93 | V | | 5 |
| VIN under-voltage protection hysteresis | VUVP_HYS | 120 | 200 | 280 | mV | | 5 |
| Input voltage regulation range (MIVR) | VMIVR | 3.9 | | 13.4 | V | I2C programmable per 0.1V | 5 |
| VMIVR accuracy | VMIVR_ACC | -3 | | 3 | % | MIVR = 4.4V, 9V | 6 |
| IC active threshold voltage (VIN UVLO) | VUVLO | 3.05 | 3.3 | 3.55 | V | VIN rising | 6 |
| VIN OVP threshold voltage | VINOVP | 13.5 | 14.5 | 15.5 | V | VIN rising | 6 |
| Battery OVP | VBATOVP | 102 | 104 | 106 | % | | 6 |
| Battery UVP | VBATUVP | 2.3 | 2.4 | 2.5 | V | VBAT falling | 6 |
| Battery voltage regulation (end of charge) | VOREG | 3.8 | | 5.06 | V | I2C programmable per 20mV | 6 |
| Battery voltage accuracy | VOREG_ACC | -1 | | 1 | % | Temperature = 0 to 85°C | 6 |
| Charging current | ICHG | 0.6 | | 3 | A | I2C programmable per 0.1A | 6 |
| ICHG accuracy | ICHG_ACC | -15 | | 15 | % | VIN = 5V, charge current > 1A | 6 |
| ICHG accuracy | ICHG_ACC | -10 | | 10 | % | VIN = 9V, 12V, charge current > 1A | 6 |
| ICHG accuracy | ICHG_ACC | -150 | | 150 | mA | VIN = 5V, charge current < 1A | 6 |
| ICHG accuracy | ICHG_ACC | -100 | | 100 | mA | VIN = 9V, 12V, charge current < 1A | 6 |
| End of charging current | IEOC | 0.6 | | 1.6 | A | I2C programmable per 0.1A | 6 |
| IEOC accuracy | IEOC_ACC | -15 | | 15 | % | VIN = 5V, 9V, 12V, IEOC setting > 1A | 6 |
| IEOC accuracy | IEOC_ACC | -150 | | 150 | mA | VIN = 5V, 9V, 12V, IEOC setting < 1A | 6 |
| High-side on-resistance | RON(Q1) | 17 | 21.5 | 26 | mΩ | From VIN to SW | 6 |
| Low-side on-resistance | RON(Q2) | 17 | 21.5 | 26 | mΩ | From SW to PGND | 6 |
| Switching frequency (1.5MHz) | fOSC1 | 1.35 | 1.5 | 1.65 | MHz | I2C programmable 1.5 MHz | 6 |
| Switching frequency (750kHz) | fOSC2 | 0.675 | 0.75 | 0.825 | MHz | I2C programmable 0.75MHz | 6 |
| Frequency accuracy | | -10 | | 10 | % | | 7 |
| Minimum duty cycle | | 0 | | | % | | 7 |
| VREG regulation | VREG | 4.74 | 4.9 | 5.06 | V | VIN = 5V | 7 |
| EN pull-low resistance | REN | 180 | 500 | 820 | kΩ | | 7 |
| I2C output low voltage | VOL | | | 0.4 | V | IDS = 10mA | 7 |
| SCL, SDA input logic high threshold voltage | VIH | 1.3 | | | V | | 7 |
| SCL, SDA input logic low threshold voltage | VIL | | | 0.4 | V | | 7 |
| SCL clock | | | | 400 | kHz | | 7 |
| Load capacitance | CLOAD | | | 1 | pF | VPULL_UP = 1.8V | 7 |
| Junction temperature monitor accuracy | | -3 | | 3 | °C | | 7 |
| EN input threshold voltage (high) | VIH | 1.2 | | | V | Logic high threshold | 7 |
| EN input threshold voltage (low) | VIL | | | 0.4 | V | Logic low threshold | 7 |
| Device turn-on delay time after EN pull-high | | | | 500 | µs | After EN pull-High | 7 |
| Supply input voltage (recommended) | VIN | 3.9 | | 14 | V | | 5 |
| Charge current (recommended) | IBAT | 0.6 | | 3 | A | | 5 |
| Battery voltage (recommended) | VBAT | 3.8 | | 5.06 | V | | 5 |
| Junction temperature range (recommended) | | -40 | | 125 | °C | | 5 |
| Ambient temperature range (recommended) | | -40 | | 85 | °C | | 5 |
| Supply input voltage (absolute maximum) | VIN | -0.3 | | 22 | V | | 5 |
| BOOT (absolute maximum) | | -0.3 | | 22 | V | | 5 |
| SW (absolute maximum) | | -0.3 | | 20 | V | | 5 |
| REG, SCL, SDA, EN, INT, BAT+, BAT- (absolute maximum) | | -0.3 | | 6 | V | | 5 |
| ESD susceptibility HBM | | | | 2 | kV | | 5 |
| Lead temperature (soldering, 10 sec) | | | | 260 | °C | | 5 |
| Junction temperature (absolute maximum) | | | | 150 | °C | | 5 |
| Storage temperature range | | -65 | | 150 | °C | | 5 |
| Power dissipation, WQFN-16L 3x3 | PD | | | 3.33 | W | TA = 25°C | 5 |
| Package thermal resistance, junction-to-ambient, WQFN-16L 3x3 | θJA | | 30 | | °C/W | | 5 |
| Package thermal resistance, junction-to-case, WQFN-16L 3x3 | θJC | | 7.5 | | °C/W | | 5 |
## CAD (KiCad official)
- Symbol: `RT9465GQW`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `rt9465gqw-etched.step` / `rt9465gqw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt9465gqw.step` / `rt9465gqw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Richtek Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590234455647686656) (25 pp, sha256 `e2a57a4fd80e8c64`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/rt9465gqw-datasheet.pdf)