component
RT9166-18GVL
Public Made by Adomby adom
Richtek Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-3L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownRT9166-18GVL
Richtek Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-3L
RT9166-18GVL from Richtek Tech, in a SOT-23-3L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Common ground; the SOT-23-3 (L-Type) top view places GND at the bottom-left pin beside the pin-1 marker. |
| 2 | VOUT | power_out | Regulator output, fixed 1.8V for the -18 option, with a minimum 1uF ceramic output capacitor recommended and 300mA minimum current limit for RT9166. |
| 3 | VIN | power_in | Supply input, recommended 2.8V to 5.5V (absolute maximum 6.5V), with an approximately 1uF input capacitor placed within 1 cm. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOT-23-3L |
| Category | Power Management (PMIC) |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage Accuracy | VOUT | 1 | 3 | % | IOUT = 1mA | 3 | |
| Current Limit (RT9166) | ILIM | 300 | mA | RLOAD = 1 | 3 | ||
| Quiescent Current | IQ | 220 | 300 | μA | IOUT = 0mA | 3 | |
| Dropout Voltage (RT9166) | VDROP | 230 | mV | IOUT = 300mA | 3 | ||
| Line Regulation | VLINE | 0.2 | %/V | VIN = (VOUT + 0.3V) to 5.5V, IOUT = 1mA | 3 | ||
| Load Regulation (RT9166) | VLOAD | 15 | 35 | mV | 1mA ≤ IOUT ≤ 300mA | 3 | |
| Power Supply Rejection Rate | PSRR | 55 | dB | f = 1kHz, COUT = 1F | 4 | ||
| Thermal Shutdown Temperature | TSD | 170 | °C | 4 | |||
| Thermal Shutdown Hysteresis | TSD | 40 | °C | 4 | |||
| Supply Input Voltage | VIN | 2.8 | 5.5 | V | 3 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 3 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 3 | ||
| Output Capacitor (ceramic, X7R or X5R) | COUT | 1 | 4.7 | μF | Recommended range between LDO output and GND | 8 | |
| Output Capacitor ESR | ESR | 10 | 50 | mΩ | Ceramic output capacitor between LDO output and GND | 8 | |
| Supply Input Voltage | VIN | 6.5 | V | 3 | |||
| Power Dissipation, SOT-23-3 | PD | 0.4 | W | TA = 25°C | 3 | ||
| Junction Temperature | TJ | 150 | °C | 3 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 3 | ||
| Lead Temperature (Soldering) | TLEAD | 260 | °C | 10 sec | 3 | ||
| ESD Susceptibility HBM | ESD | 2 | kV | Human Body Model | 3 | ||
| Package Thermal Resistance, Junction-to-Ambient | θJA | 250 | °C/W | SOT-23-3, JEDEC 51-3 single-layer test board | 3 |
CAD (KiCad official)
- Symbol:
RT9166-18GVL - Footprint:
Package_TO_SOT_SMD:SOT-23-3 - 3D model: SOT-23-3L (KiCad packages3D, STEP)
- 3D model files:
rt9166-18gvl-etched.step/rt9166-18gvl-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt9166-18gvl.step/rt9166-18gvl.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (16 pp, sha256
1d9800fc32250eea, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).