component
RT9078-30GJ5
Public Made by Adomby adom
Richtek Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TSOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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RT9078-30GJ5
Richtek Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TSOT-23-5
RT9078-30GJ5 from Richtek Tech, in a TSOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Regulator input pin, with the input capacitor to be placed directly at this pin; the input voltage range is 1.2V to 5.5V. |
| 2 | GND | power_in | Ground reference pin for the regulator. |
| 3 | EN | input | Chip enable pin: pulling it below 0.4V turns the regulator off and reduces quiescent current to a fraction of its operating value, and above 0.9V turns the regulator on. |
| 4 | NC | unconnected | No internal connection on the RT9078 (the SNS output-voltage sense function on this pin applies only to the RT9078N variant). |
| 5 | VOUT | power_out | Regulator output pin, with the output capacitor to be placed directly at this pin; a minimum of 1µF output capacitance is required for stable operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | TSOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 1.2 | 5.5 | V | 5 | ||
| Junction Temperature Range | -40 | 125 | °C | 5 | |||
| Output capacitor ESR (application text) | 1 | mΩ | Any output capacitor used; minimum ESR | 12 | |||
| Input capacitor (application text) | 1 | µF | Input capacitor placed close to VIN and GND | 12 | |||
| Output capacitance (application text) | 1 | µF | Output capacitor; capacitance larger than 1µF | 12 | |||
| Effective output capacitance at targeted output level (Table 1 note) | 0.7 | µF | Effective capacitance at targeted output level, derated with bias | 7 | |||
| VIN, VOUT, SNS, EN to GND | -0.3 | 6.5 | V | 5 | |||
| VOUT to VIN | -6.5 | 0.3 | V | 5 | |||
| Power Dissipation (TSOT-23-5) | PD | 0.43 | W | TA = 25°C, TSOT-23-5 | 5 | ||
| Package Thermal Resistance junction-to-ambient (TSOT-23-5) | θJA | 230.6 | °C/W | TSOT-23-5, JEDEC 51-7 four-layer test board, TA = 25°C | 5 | ||
| Package Thermal Resistance junction-to-case (TSOT-23-5) | θJC | 21.8 | °C/W | TSOT-23-5 | 5 | ||
| Lead Temperature (Soldering, 10 sec.) | 260 | °C | Soldering, 10 sec | 5 | |||
| Junction Temperature | 150 | °C | 5 | ||||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| ESD Susceptibility HBM | 2 | kV | Human Body Model | 5 | |||
| Fixed Output Voltage Range | VOUT | 0.8 | 3.45 | V | 5 | ||
| DC Output Accuracy | -2 | 2 | % | ILOAD = 1mA | 5 | ||
| Dropout Voltage (3V ≤ VOUT row) | VDROP | 0.15 | 0.2 | V | ILOAD = 300mA (Note 5); 3V ≤ VOUT | 5 | |
| VCC Consumption Current | IQ | 2 | 4 | µA | ILOAD = 0mA; VOUT ≤ 5.5V; VIN ≥ VOUT + VDROP | 5 | |
| Shutdown GND Current | 0.1 | 0.5 | µA | VEN = 0V | 6 | ||
| Shutdown Leakage Current | 0.1 | 0.5 | µA | VEN = 0V, VOUT = 0V | 6 | ||
| EN Input Current | IEN | 0.1 | µA | VEN = 5.5V | 6 | ||
| Line Regulation (1.2V to 1.5V VIN) | LINE | 0.3 | 0.6 | % | ILOAD = 1mA; 1.2V ≤ VIN ≤ 1.5V | 6 | |
| Line Regulation (1.5V to 1.8V VIN) | LINE | 0.15 | 0.3 | % | ILOAD = 1mA; 1.5V ≤ VIN ≤ 1.8V | 6 | |
| Line Regulation (1.8V to 5.5V VIN) | LINE | 0.13 | 0.35 | % | ILOAD = 1mA; 1.8V ≤ VIN ≤ 5.5V | 6 | |
| Load Regulation | LOAD | 0.5 | 1 | % | 1mA < ILOAD < 300mA | 6 | |
| Output Current Limit | ILIM | 350 | 600 | mA | VOUT = 90% of VOUT(NOM) | 6 | |
| Enable Threshold Voltage H-Level | VENH | 0.5 | 0.7 | 0.9 | V | VIN = 5V | 6 |
| Enable Threshold Voltage L-Level | VENL | 0.4 | 0.65 | 0.85 | V | VIN = 5V | 6 |
CAD (KiCad official)
- Symbol:
RT9078-30GJ5 - Footprint:
Package_TO_SOT_SMD:TSOT-23-5 - 3D model: TSOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
rt9078-30gj5-etched.step/rt9078-30gj5-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt9078-30gj5.step/rt9078-30gj5.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (16 pp, sha256
58b21b14eba5e089, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).