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RT9059GSP

Public Made by Adom

by adom

Richtek Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs rt9059gsp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json rt9059gsp: specified limits as data (metadata.characteristics, 42 rows from the datasheet) · Ray
README.md rt9059gsp: specified limits as data (metadata.characteristics, 42 rows from the datasheet) · Ray
rt9059gsp-etched.fit.json rt9059gsp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
rt9059gsp-etched.glb rt9059gsp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
rt9059gsp-etched.step rt9059gsp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
rt9059gsp.glb fix footprint: SOIC-8_3.9x4.9mm_P1.27mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm (ep_dropped, 8 pins; datasheet EP 2.… · Ray
rt9059gsp.kicad_mod fix footprint: SOIC-8_3.9x4.9mm_P1.27mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm (ep_dropped, 8 pins; datasheet EP 2.… · Ray
rt9059gsp.kicad_sym Publish 0.1.0 · Ray
rt9059gsp.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
rt9059gsp.step fix footprint: SOIC-8_3.9x4.9mm_P1.27mm -> SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm (ep_dropped, 8 pins; datasheet EP 2.… · Ray

RT9059GSP

Richtek Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOP-8-EP

RT9059GSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGOOD output Power good open-drain output. Asserts (high-Z) when VOUT reaches 90% of its rated value (10% falling hysteresis) after a 1ms typical delay. Requires an external pull-up resistor; sink capability 0.2V @ 10mA.
2 EN input Enable control input. Logic-high (VIH >= 1.2V) enables the regulator; logic-low (VIL <= 0.4V) shuts it down and pulls VOUT low through ~150Ω. Absolute maximum -0.3V to 6V.
3 VIN power_in Supply input voltage; source of the regulated output current up to 3A. Operating range 1V to 5.5V. Bypass with a 10μF ceramic capacitor to GND close to the pin.
4 VDD power_in Supply voltage of the internal control circuit. Must satisfy VDD > VOUT + 1.5V; operating range 3V to 5.5V. Bypass with a 1μF ceramic capacitor to GND.
5 NC unconnected No internal connection. May be left floating or tied to GND for board layout convenience.
6 VOUT power_out Regulated output voltage, up to 3A load current. Dropout typically 350mV at 3A. Requires a 10μF ceramic output capacitor to GND.
7 ADJ input Output voltage feedback / setting input for the adjustable version. VOUT = VREF x (R1 + R2) / R2, with VREF = 0.8V typical. Connect the mid-point of the external R1/R2 divider from VOUT to GND.
8 GND power_in Ground return for the device. Pin 8 and the exposed pad (pin 9) are internally tied to GND.
9 GND (Exposed Pad) power_in Exposed thermal pad. Must be soldered to a large PCB copper area connected to GND for maximum power dissipation (θJC = 6.5°C/W, PD = 3.08W @ 25°C).

Key specifications

Parameter Value
Manufacturer Richtek Tech
Package SOP-8-EP
Category PMIC
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • RT9059GSP
  • RT9059-15GSP
  • RT9059-18GSP
  • RT9059-25GSP
  • RT9059GQW
  • RT9059-15GQW
  • RT9059-18GQW
  • RT9059-25GQW

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD Operation Range VDD 3 5.5 V 4
VDD POR Threshold VPOR_VDD 2.4 2.7 3 V VDD rising 4
VDD POR Falling Hysteresis VPOR_VDD 0.15 0.2 V VDD falling 4
Input Voltage Range VIN 1 5.5 V 4
VIN POR Threshold VPOR_VIN 0.7 0.8 0.9 V VIN rising 4
VIN POR Falling Hysteresis VPOR_VIN 0.15 0.2 0.25 V VIN falling 4
Quiescent Current IQ 0.6 1.2 mA EN on, no load 4
Reference Voltage VREF 0.788 0.8 0.812 V 5
VOUT Load Regulation VLOAD 0.5 1 % IOUT = 1mA to 3A, VIN = VOUT + 1V 5
VOUT Line Regulation VLINE 0.2 0.6 % VDD = 3.6V to 5.5V, VIN = VOUT + 1V to 5V, IOUT = 1mA 5
Dropout Voltage VDROP 250 350 mV IOUT = 2A 5
Dropout Voltage VDROP 350 450 mV IOUT = 3A 5
Current Limit ILIM 3.1 3.6 4.2 A VIN = 3.6V 5
Short Circuit Current ISC 1 1.4 1.8 A VOUT < 0.2V 5
PGOOD Delay Time 0.2 1 1.5 ms 5
PGOOD Sink Capability VPGOOD 0.2 0.4 V ISINK = 10mA 5
EN Input Logic-High VIH 1.2 V 5
EN Input Logic-Low VIL 0.4 V 5
EN Delay Time 0.3 0.85 1.4 ms 5
VDD Pin Shutdown Current ISHDN_VDD 1 A VEN = 0V 5
VIN Pin Shutdown Current ISHDN_VIN 1 A VEN = 0V, VIN = 5V 5
Soft-Start Time tSS 1.9 2.8 3.75 ms 5
Input Voltage, VIN to GND (DC) VIN -0.3 6 V DC 4
Input Voltage, VIN to GND (<10ms) VIN -0.3 7 V < 10ms 4
Control Voltage, VDD to GND (DC) VDD -0.3 6 V DC 4
Control Voltage, VDD to GND (<10ms) VDD -0.3 7 V < 10ms 4
Output Voltage VOUT -0.3 6 V 4
Chip Enable Voltage EN -0.3 6 V 4
Adjust Voltage ADJ -0.3 6 V 4
Power Good Voltage VPGOOD -0.3 6 V 4
Power Dissipation, SOP-8 (Exposed Pad) PD 3.08 W TA = 25°C 4
Junction Temperature 150 °C 4
Storage Temperature Range -65 150 °C 4
Lead Temperature 260 °C Soldering, 10 sec. 4
ESD Susceptibility HBM 2 kV HBM (Human Body Model) 4
ESD Susceptibility MM 200 V MM (Machine Model) 4
Supply Input Voltage VIN 1 5.5 V 4
Control Voltage VDD 3 5.5 V VDD > VOUT + 1.5V 4
Junction Temperature Range -40 125 °C 4
Ambient Temperature Range -40 85 °C 4
Package Thermal Resistance, junction to ambient (SOP-8 EP) θJA 32.4 °C/W Note 2: JEDEC 51-7 four-layer board, TA = 25°C 4
Package Thermal Resistance, junction to case (SOP-8 EP) θJC 6.5 °C/W Note 2: measured at exposed pad 4

CAD (KiCad official)

  • Symbol: RT9059GSP
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOP-8-EP (KiCad packages3D, STEP)
  • 3D model files: rt9059gsp-etched.step / rt9059gsp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rt9059gsp.step / rt9059gsp.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
rt9059gsp.step 125 KB You want the bare part, or you mark your own boards.
rt9059gsp-etched.step 2.3 MB You want the part with RT9059GSP already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 557 faces against 152 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Richtek Tech datasheet (12 pp, sha256 498869c640dbc9f4, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF