component
RT9059GSP
Public Made by Adomby adom
Richtek Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
5 files changed
+460−146
package.json+2−1@@ -24,6 +24,7 @@ "docs/hero.png", "docs/rt9059gsp-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ] }
pads.jsonadded+302@@ -0,0 +1,302 @@+{+ "schema": "adom.pads/1",+ "slug": "rt9059gsp",+ "footprint": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm",+ "generated_from": {+ "footprint": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm@sha256:a7971720bdda0353",+ "pins": "page.json:component.pins",+ "overrides": null+ },+ "pin1": {+ "pad": "1",+ "at": [+ -2.475,+ -1.905+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm@sha256:a7971720bdda0353"+ },+ "pad_count": 9,+ "symbol_pins": [+ "1",+ "2",+ "3",+ "4",+ "5",+ "6",+ "7",+ "8",+ "9"+ ],+ "paste_apertures": 4,+ "issues": [],+ "pads": [+ {+ "pad": "1",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "1",+ "name": "PGOOD",+ "type": "output",+ "description": "Power good open-drain output. Asserts (high-Z) when VOUT reaches 90% of its rated value (10% falling hysteresis) after a 1ms typical delay. Requires an external pull-up resistor; sink capability 0.2V @ 10mA.",+ "is_pin1": true,+ "source": {+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "2",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "2",+ "name": "EN",+ "type": "input",+ "description": "Enable control input. Logic-high (VIH >= 1.2V) enables the regulator; logic-low (VIL <= 0.4V) shuts it down and pulls VOUT low through ~150Ω. Absolute maximum -0.3V to 6V.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "3",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "3",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input voltage; source of the regulated output current up to 3A. Operating range 1V to 5.5V. Bypass with a 10μF ceramic capacitor to GND close to the pin.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "4",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "4",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage of the internal control circuit. Must satisfy VDD > VOUT + 1.5V; operating range 3V to 5.5V. Bypass with a 1μF ceramic capacitor to GND.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "5",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "5",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection. May be left floating or tied to GND for board layout convenience.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "6",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "6",+ "name": "VOUT",+ "type": "power_out",+ "description": "Regulated output voltage, up to 3A load current. Dropout typically 350mV at 3A. Requires a 10μF ceramic output capacitor to GND.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "7",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "7",+ "name": "ADJ",+ "type": "input",+ "description": "Output voltage feedback / setting input for the adjustable version. VOUT = VREF x (R1 + R2) / R2, with VREF = 0.8V typical. Connect the mid-point of the external R1/R2 divider from VOUT to GND.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "8",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground return for the device. Pin 8 and the exposed pad (pin 9) are internally tied to GND.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "9",+ "kind": "smd",+ "shape": "rect",+ "at": [+ 0.0,+ 0.0+ ],+ "rot": 0.0,+ "size": [+ 2.29,+ 3.0+ ],+ "layers": [],+ "thermal": true,+ "pin": "9",+ "name": "GND (Exposed Pad)",+ "type": "power_in",+ "description": "Exposed thermal pad. Must be soldered to a large PCB copper area connected to GND for maximum power dissipation (θJC = 6.5°C/W, PD = 3.08W @ 25°C).",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ }+ ]+}
page.json+154−143@@ -1,148 +1,159 @@ {- "schema_version": 1,- "type": "component",- "slug": "rt9059gsp",- "title": "RT9059GSP",- "brief": "Richtek Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOP-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",- "license": "CC-BY-SA-4.0",- "tags": [- "component",- "pmic",- "rt9059gsp"- ],- "component": {- "mpn": "RT9059GSP",- "manufacturer": "Richtek Tech",- "package": "SOP-8-EP",- "pin_count": 9,- "category": "PMIC",- "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",- "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2203221830_Richtek-Tech-RT9059GSP_C425783.pdf",- "parts": {- "symbol": "rt9059gsp.kicad_sym",- "footprint": "rt9059gsp.kicad_mod",- "model_3d": "rt9059gsp.glb",- "model_3d_step": "rt9059gsp.step",- "lbr": "rt9059gsp.lbr"+ "schema_version": 1,+ "type": "component",+ "slug": "rt9059gsp",+ "title": "RT9059GSP",+ "brief": "Richtek Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOP-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "version": "0.1.0",+ "license": "CC-BY-SA-4.0",+ "tags": [+ "component",+ "pmic",+ "rt9059gsp"+ ],+ "component": {+ "mpn": "RT9059GSP",+ "manufacturer": "Richtek Tech",+ "package": "SOP-8-EP",+ "pin_count": 9,+ "category": "PMIC",+ "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2203221830_Richtek-Tech-RT9059GSP_C425783.pdf",+ "parts": {+ "symbol": "rt9059gsp.kicad_sym",+ "footprint": "rt9059gsp.kicad_mod",+ "model_3d": "rt9059gsp.glb",+ "model_3d_step": "rt9059gsp.step",+ "lbr": "rt9059gsp.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "PGOOD",+ "type": "output",+ "description": "Power good open-drain output. Asserts (high-Z) when VOUT reaches 90% of its rated value (10% falling hysteresis) after a 1ms typical delay. Requires an external pull-up resistor; sink capability 0.2V @ 10mA."+ },+ {+ "number": "2",+ "name": "EN",+ "type": "input",+ "description": "Enable control input. Logic-high (VIH >= 1.2V) enables the regulator; logic-low (VIL <= 0.4V) shuts it down and pulls VOUT low through ~150Ω. Absolute maximum -0.3V to 6V."+ },+ {+ "number": "3",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input voltage; source of the regulated output current up to 3A. Operating range 1V to 5.5V. Bypass with a 10μF ceramic capacitor to GND close to the pin."+ },+ {+ "number": "4",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage of the internal control circuit. Must satisfy VDD > VOUT + 1.5V; operating range 3V to 5.5V. Bypass with a 1μF ceramic capacitor to GND."+ },+ {+ "number": "5",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection. May be left floating or tied to GND for board layout convenience."+ },+ {+ "number": "6",+ "name": "VOUT",+ "type": "power_out",+ "description": "Regulated output voltage, up to 3A load current. Dropout typically 350mV at 3A. Requires a 10μF ceramic output capacitor to GND."+ },+ {+ "number": "7",+ "name": "ADJ",+ "type": "input",+ "description": "Output voltage feedback / setting input for the adjustable version. VOUT = VREF x (R1 + R2) / R2, with VREF = 0.8V typical. Connect the mid-point of the external R1/R2 divider from VOUT to GND."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground return for the device. Pin 8 and the exposed pad (pin 9) are internally tied to GND."+ },+ {+ "number": "9",+ "name": "GND (Exposed Pad)",+ "type": "power_in",+ "description": "Exposed thermal pad. Must be soldered to a large PCB copper area connected to GND for maximum power dissipation (θJC = 6.5°C/W, PD = 3.08W @ 25°C)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2203221830_Richtek-Tech-RT9059GSP_C425783.pdf",+ "pages": 12,+ "sha256": "498869c640dbc9f4",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 9,+ "described": 9,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "pin1": {+ "pad": "1",+ "at": [+ -2.475,+ -1.905+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm@sha256:a7971720bdda0353",+ "mark": "drawn"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Unknown",+ "Package": "SOP-8-EP",+ "Category": "PMIC",+ "Pins": "9"+ } },- "distributor_links": {},- "pins": [- {- "number": "1",- "name": "PGOOD",- "type": "output",- "description": "Power good open-drain output. Asserts (high-Z) when VOUT reaches 90% of its rated value (10% falling hysteresis) after a 1ms typical delay. Requires an external pull-up resistor; sink capability 0.2V @ 10mA."- },- {- "number": "2",- "name": "EN",- "type": "input",- "description": "Enable control input. Logic-high (VIH >= 1.2V) enables the regulator; logic-low (VIL <= 0.4V) shuts it down and pulls VOUT low through ~150\u03a9. Absolute maximum -0.3V to 6V."- },- {- "number": "3",- "name": "VIN",- "type": "power_in",- "description": "Supply input voltage; source of the regulated output current up to 3A. Operating range 1V to 5.5V. Bypass with a 10\u03bcF ceramic capacitor to GND close to the pin."- },- {- "number": "4",- "name": "VDD",- "type": "power_in",- "description": "Supply voltage of the internal control circuit. Must satisfy VDD > VOUT + 1.5V; operating range 3V to 5.5V. Bypass with a 1\u03bcF ceramic capacitor to GND."- },- {- "number": "5",- "name": "NC",- "type": "unconnected",- "description": "No internal connection. May be left floating or tied to GND for board layout convenience."- },- {- "number": "6",- "name": "VOUT",- "type": "power_out",- "description": "Regulated output voltage, up to 3A load current. Dropout typically 350mV at 3A. Requires a 10\u03bcF ceramic output capacitor to GND."- },- {- "number": "7",- "name": "ADJ",- "type": "input",- "description": "Output voltage feedback / setting input for the adjustable version. VOUT = VREF x (R1 + R2) / R2, with VREF = 0.8V typical. Connect the mid-point of the external R1/R2 divider from VOUT to GND."- },- {- "number": "8",- "name": "GND",- "type": "power_in",- "description": "Ground return for the device. Pin 8 and the exposed pad (pin 9) are internally tied to GND."- },- {- "number": "9",- "name": "GND (Exposed Pad)",- "type": "power_in",- "description": "Exposed thermal pad. Must be soldered to a large PCB copper area connected to GND for maximum power dissipation (\u03b8JC = 6.5\u00b0C/W, PD = 3.08W @ 25\u00b0C)."- }+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info" ],- "provenance": {- "extractor": "ds2sf",- "datasheet": {- "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2203221830_Richtek-Tech-RT9059GSP_C425783.pdf",- "pages": 12,- "sha256": "498869c640dbc9f4",- "source_tier": "lcsc"- },- "cad": "KiCad official (CC-BY-SA 4.0)",- "pins": {- "total": 9,- "described": 9,- "cites_pages": true,- "refuses_to_fabricate": true- }+ "discovery_triggers": [+ "rt9059gsp"+ ],+ "discovery_pitch": "RT9059GSP (Unknown) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ },+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png" },- "viewers": {- "symbol": "viewers/symbol.html",- "footprint": "viewers/footprint.html"- }- },- "metadata": {- "specs": {- "Manufacturer": "Unknown",- "Package": "SOP-8-EP",- "Category": "PMIC",- "Pins": "9"- }- },- "sections": [- "hero",- "viewers",- "readme",- "breadcrumbs",- "info"- ],- "discovery_triggers": [- "rt9059gsp"- ],- "discovery_pitch": "RT9059GSP (Unknown) component page with datasheet-verified CAD.",- "author": {- "name": "Ray",- "email": "[email protected]"- },- "dependencies": {},- "hero": {- "type": "image",- "path": "docs/hero.png"- },- "files": [- "page.json",- "README.md",- "rt9059gsp.kicad_sym",- "rt9059gsp.kicad_mod",- "rt9059gsp.glb",- "rt9059gsp.step",- "rt9059gsp.lbr",- "docs/hero.png",- "docs/rt9059gsp-datasheet.pdf",- "viewers/symbol.html",- "viewers/footprint.html"- ]+ "files": [+ "page.json",+ "README.md",+ "rt9059gsp.kicad_sym",+ "rt9059gsp.kicad_mod",+ "rt9059gsp.glb",+ "rt9059gsp.step",+ "rt9059gsp.lbr",+ "docs/hero.png",+ "docs/rt9059gsp-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ] }
rt9059gsp.lbr+1−1@@ -71,7 +71,7 @@ <wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/> <text x="0" y="3.480" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-3.480" size="1.27" layer="27" align="top-center">>VALUE</text>-</package>+<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package> </packages> <symbols> <symbol name="RT9059GSP">
viewers/footprint.html+1−1@@ -23,7 +23,7 @@ rect.pad.hi{stroke:var(--hi);stroke-width:.15;paint-order:stroke} #tip .td{font-size:11px;color:var(--ink);margin-top:5px;line-height:1.4} </style></head><body> <div class=bar><span class=h>PCB footprint</span><span class=sp></span><button class="lyrtog on" data-lyr="copper"><span class="d" style="background:#e35d5d"></span>Copper</button><button class="lyrtog on" data-lyr="silk"><span class="d" style="background:#e6edf3"></span>Silkscreen</button><button class="lyrtog" data-lyr="fab"><span class="d" style="background:#8b949e"></span>Fab</button><button class="lyrtog" data-lyr="courtyard"><span class="d" style="background:#bc8cff"></span>Courtyard</button></div>-<div class=stage id=stage><svg xmlns='http://www.w3.org/2000/svg' viewBox='-4.100 -3.100 8.200 6.200' style='width:100%;height:100%'><line class='ly-silk' x1='-2.060' y1='-2.560' x2='2.060' y2='-2.560' stroke='#d8b4fe' stroke-width='0.120'/><line class='ly-silk' x1='-2.060' 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