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RT9059GQW
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Richtek Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WDFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+103@@ -0,0 +1,103 @@+# RT9059GQW++**Richtek Tech** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WDFN-10(3x3)++RT9059GQW from Richtek Tech, in a WDFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VOUT | power_out | Regulated output voltage; in adjustable mode VOUT is set between 0.8V and VIN by the external divider on ADJ. |+| 2 | VOUT | power_out | Regulated output voltage (pin 2 is tied to the same VOUT net as pins 1 and 3); the datasheet recommends a low-ESR ceramic output capacitor of at least 10µF located within 0.5 inch of the VOUT pin. |+| 3 | VOUT | power_out | Regulated output voltage (pin 3 is tied to the same VOUT net as pins 1 and 2); the datasheet recommends a low-ESR ceramic output capacitor of at least 10µF located within 0.5 inch of the VOUT pin. |+| 4 | ADJ | input | Output voltage setting; VOUT = VREF x (R1+R2)/R2 with VREF 0.8V typical, and R1/R2 should each be more than 10kΩ to limit power loss. |+| 5 | PGOOD | output | Open-drain power good output that goes high when VOUT reaches 90% of its nominal value; the datasheet specifies a 100kΩ pull-up to VOUT and sink voltage of 0.4V max at 10mA. |+| 6 | EN | input | Enable control input: logic high at 1.2V min and logic low at 0.4V max; the pin is pulled low internally, so the regulator is off when EN is floating. |+| 7 | VIN | power_in | Supply input voltage, 1V to 5.5V recommended; a 10µF or larger input capacitor placed close to the IC is recommended. |+| 8 | VIN | power_in | Supply input voltage, 1V to 5.5V recommended (pin 8 is tied to the same VIN net as pins 7 and 9). |+| 9 | VIN | power_in | Supply input voltage, 1V to 5.5V recommended (pin 9 is tied to the same VIN net as pins 7 and 8). |+| 10 | VDD | power_in | Supply voltage of the control circuit, 3V to 5.5V; VDD must be greater than VOUT + 1.5V. |+| 11 | GND | power_in | Ground; the exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Richtek Tech |+| Package | WDFN-10(3x3) |+| Category | Power Management (PMIC) |+| Pins | 11 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Supply Input Voltage, VIN | VIN | 1 | | 5.5 | V | | 4 |+| Control Voltage, VDD | VDD | 3 | | 5.5 | V | VDD > VOUT + 1.5V | 4 |+| Junction Temperature Range | | -40 | | 125 | °C | | 4 |+| Ambient Temperature Range | | -40 | | 85 | °C | | 4 |+| Supply Input Voltage, VIN to GND (DC) | VIN | -0.3 | | 6 | V | DC | 4 |+| Supply Input Voltage, VIN to GND (<10ms) | VIN | -0.3 | | 7 | V | < 10ms | 4 |+| Control Voltage, VDD to GND (DC) | VDD | -0.3 | | 6 | V | DC | 4 |+| Control Voltage, VDD to GND (<10ms) | VDD | -0.3 | | 7 | V | < 10ms | 4 |+| Output Voltage | VOUT | -0.3 | | 6 | V | | 4 |+| Chip Enable Voltage | EN | -0.3 | | 6 | V | | 4 |+| Adjust Voltage | ADJ | -0.3 | | 6 | V | | 4 |+| Power Good Voltage | VPGOOD | -0.3 | | 6 | V | | 4 |+| Power Dissipation, WDFN-10L 3x3 | PD | | | 2.95 | W | TA = 25°C | 4 |+| Junction Temperature | | | | 150 | °C | | 4 |+| Lead Temperature (Soldering, 10 sec.) | | | | 260 | °C | 10 sec. | 4 |+| Storage Temperature Range | | -65 | | 150 | °C | | 4 |+| ESD Susceptibility HBM (Human Body Model) | | | | 2 | kV | | 4 |+| ESD Susceptibility MM (Machine Model) | | | | 200 | V | | 4 |+| VDD Operation Range | VDD | 3 | | 5.5 | V | | 4 |+| VDD POR Threshold | VPOR_VDD | 2.4 | 2.7 | 3 | V | VDD Rising | 4 |+| VDD POR Falling Hysteresis | VPOR_VDD | 0.15 | 0.2 | | V | VDD Falling | 4 |+| Input Voltage Range | VIN | 1 | | 5.5 | V | | 4 |+| VIN POR Threshold | VPOR_VIN | 0.7 | 0.8 | 0.9 | V | VIN Rising | 4 |+| VIN POR Falling Hysteresis | VPOR_VIN | 0.15 | 0.2 | 0.25 | V | VIN Falling | 4 |+| Quiescent Current | IQ | | 0.6 | 1.2 | mA | EN On, No Load | 4 |+| Reference Voltage | VREF | 0.788 | 0.8 | 0.812 | V | | 5 |+| VOUT Load Regulation | VLOAD | | 0.5 | 1 | % | IOUT = 1mA to 3A, VIN = VOUT+1V | 5 |+| OUT Line Regulation | VLINE | | 0.2 | 0.6 | % | VDD = 3.6V to 5.5V, VIN = VOUT+1V to 5V, IOUT = 1mA | 5 |+| Dropout Voltage | VDROP | | 250 | 350 | mV | IOUT = 2A | 5 |+| Dropout Voltage | VDROP | | 350 | 450 | mV | IOUT = 3A | 5 |+| Current Limit | ILIM | 3.1 | 3.6 | 4.2 | A | VIN = 3.6V | 5 |+| Short Circuit Current | ISC | 1 | 1.4 | 1.8 | A | VOUT < 0.2V | 5 |+| PGOOD Delay Time | | | 1 | 1.5 | ms | | 5 |+| PGOOD Sink Capability | VPGOOD | | 0.2 | 0.4 | V | ISINK = 10mA | 5 |+| EN Input Logic-High Voltage | VIH | 1.2 | | | V | | 5 |+| EN Input Logic-Low Voltage | VIL | | | 0.4 | V | | 5 |+| EN Delay Time | | 0.3 | 0.85 | 1.4 | ms | | 5 |+| VDD Pin Shutdown Current | ISHDN_VDD | | | 1 | µA | VEN = 0V | 5 |+| VIN Pin Shutdown Current | ISHDN_VIN | | | 1 | µA | VEN = 0V, VIN = 5V | 5 |+| Soft-Start Time | tSS | 1.9 | 2.8 | 3.75 | ms | | 5 |+| VOUT Pull Low Resistance | RPULL | | 150 | | | VEN = 0V | 5 |+| Thermal Shutdown Temperature | TSD | | 160 | | °C | | 5 |+| Thermal Shutdown Recovery Temperature | TSDR | | 90 | | °C | | 5 |+| PGOOD Rising Threshold | VTH_PGOOD | | 90 | | % | VOUT Rising | 5 |+| PGOOD Hysteresis | VTH_PGOOD | | 10 | | % | VOUT Falling | 5 |+| EN Pin Bias Current | IEN | | 12 | | µA | VEN = 5V | 5 |+| Inrush Current | IINRUSH | | 0.5 | | A | VOUT = 1.8V, COUT = 10µF, ILoad = 1A | 5 |+| Package Thermal Resistance, WDFN-10L 3x3, junction-to-ambient | θJA | | 33.8 | | °C/W | JEDEC 51-7 four-layer board, TA = 25°C | 4 |+| Package Thermal Resistance, WDFN-10L 3x3, junction-to-case | θJC | | 8.9 | | °C/W | measured at exposed pad | 4 |++## CAD (KiCad official)++- Symbol: `RT9059GQW`+- Footprint: `Package_DFN_QFN:WDFN-10-1EP_3x3mm_P0.5mm_EP1.8x2.5mm`+- 3D model: WDFN-10(3x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.75 mm nominal WSON height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `rt9059gqw-etched.step` / `rt9059gqw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt9059gqw.step` / `rt9059gqw.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Richtek Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881876160794624) (12 pp, sha256 `9dc0d1b51e41c0c9`, retrieved 2026-10-17, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/rt9059gqw-datasheet.pdf)
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in adjustable mode VOUT is set between 0.8V and VIN by the external divider on ADJ."+ },+ {+ "number": "2",+ "name": "VOUT",+ "type": "power_out",+ "description": "Regulated output voltage (pin 2 is tied to the same VOUT net as pins 1 and 3); the datasheet recommends a low-ESR ceramic output capacitor of at least 10µF located within 0.5 inch of the VOUT pin."+ },+ {+ "number": "3",+ "name": "VOUT",+ "type": "power_out",+ "description": "Regulated output voltage (pin 3 is tied to the same VOUT net as pins 1 and 2); the datasheet recommends a low-ESR ceramic output capacitor of at least 10µF located within 0.5 inch of the VOUT pin."+ },+ {+ "number": "4",+ "name": "ADJ",+ "type": "input",+ "description": "Output voltage setting; VOUT = VREF x (R1+R2)/R2 with VREF 0.8V typical, and R1/R2 should each be more than 10kΩ to limit power loss."+ },+ {+ "number": "5",+ "name": "PGOOD",+ "type": "output",+ "description": "Open-drain power good output that goes high when VOUT reaches 90% of its nominal value; the datasheet specifies a 100kΩ pull-up to VOUT and sink voltage of 0.4V max at 10mA."+ },+ {+ "number": "6",+ "name": "EN",+ "type": "input",+ "description": "Enable control input: logic high at 1.2V min and logic low at 0.4V max; the pin is pulled low internally, so the regulator is off when EN is floating."+ },+ {+ "number": "7",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input voltage, 1V to 5.5V recommended; a 10µF or larger input capacitor placed close to the IC is recommended."+ },+ {+ "number": "8",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input voltage, 1V to 5.5V recommended (pin 8 is tied to the same VIN net as pins 7 and 9)."+ },+ {+ "number": "9",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input voltage, 1V to 5.5V recommended (pin 9 is tied to the same VIN net as pins 7 and 8)."+ },+ {+ "number": "10",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage of the control circuit, 3V to 5.5V; VDD must be greater than VOUT + 1.5V."+ },+ {+ "number": "11",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; the exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: MPN RT9059GQW has no fixed output-voltage code (15/18/25) in its ordering string, so it is treated a; The datasheet pin table lists VOUT, VIN and GND as multiple pins sharing one net (1-3, 7-9, and expo"+ ],+ "pages_sent": 12,+ "cost_usd": 0.0669,+ "at": "2026-10-17T15:00:33"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881876160794624",+ "pages": 12,+ "sha256": "9dc0d1b51e41c0c9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 11,+ "described": 11,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "rt9059gqw.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.02,+ 3.0,+ 0.75+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "edd258a7651b5edd562fd75b5e854f4b34a54b1db5c85efafcbb7e710e786081",+ "checked": "2026-10-17",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "rt9059gqw-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.02,+ 3.0,+ 0.75+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "b19fbe55a90ae09a2e747407d6f7bfa9beb51451680d9a83e6552e53a4a0d102",+ "checked": "2026-10-17",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ }+}
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "rt9059gqw",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "rt9059gqw.kicad_sym",+ "rt9059gqw.kicad_mod",+ "rt9059gqw.glb",+ "rt9059gqw.step",+ "rt9059gqw.lbr",+ "docs/hero.png",+ "docs/rt9059gqw-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "rt9059gqw-hero.glb",+ "rt9059gqw-hero.overlay.json",+ "rt9059gqw-etched.glb"+ ],+ "component": {+ "mpn": "RT9059GQW",+ "manufacturer": "Richtek Tech",+ "package": "WDFN-10(3x3)",+ "pin_count": 11,+ "category": "Power Management (PMIC)",+ "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881876160794624",+ "parts": {+ "symbol": "rt9059gqw.kicad_sym",+ "footprint": "rt9059gqw.kicad_mod",+ "model_3d": "rt9059gqw-hero.glb",+ "model_3d_plain": "rt9059gqw-etched.glb",+ "model_3d_step": "rt9059gqw-etched.step",+ "model_3d_step_plain": "rt9059gqw.step",+ "lbr": "rt9059gqw.lbr"+ },+ "distributor_links": {+ "lcsc": "C147977"+ },+ "distributor_check": {+ "checked_at": "2026-10-17T15:02:56Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "quota"+ },+ "mouser": {+ "pn": null,+ "status": "quota"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VOUT",+ "type": "power_out",+ "description": "Regulated output voltage; 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the datasheet specifies a 100kΩ pull-up to VOUT and sink voltage of 0.4V max at 10mA."+ },+ {+ "number": "6",+ "name": "EN",+ "type": "input",+ "description": "Enable control input: logic high at 1.2V min and logic low at 0.4V max; the pin is pulled low internally, so the regulator is off when EN is floating."+ },+ {+ "number": "7",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input voltage, 1V to 5.5V recommended; a 10µF or larger input capacitor placed close to the IC is recommended."+ },+ {+ "number": "8",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input voltage, 1V to 5.5V recommended (pin 8 is tied to the same VIN net as pins 7 and 9)."+ },+ {+ "number": "9",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input voltage, 1V to 5.5V recommended (pin 9 is tied to the same VIN net as pins 7 and 8)."+ },+ {+ "number": "10",+ "name": "VDD",+ "type": "power_in",+ "description": "Supply voltage of the control circuit, 3V to 5.5V; VDD must be greater than VOUT + 1.5V."+ },+ {+ "number": "11",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; the exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: MPN RT9059GQW has no fixed output-voltage code (15/18/25) in its ordering string, so it is treated a; The datasheet pin table lists VOUT, VIN and GND as multiple pins sharing one net (1-3, 7-9, and expo"+ ],+ "pages_sent": 12,+ "cost_usd": 0.0669,+ "at": "2026-10-17T15:00:33"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881876160794624",+ "pages": 12,+ "sha256": "9dc0d1b51e41c0c9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 11,+ "described": 11,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "rt9059gqw.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.02,+ 3,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "edd258a7651b5edd562fd75b5e854f4b34a54b1db5c85efafcbb7e710e786081",+ "checked": "2026-10-17",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "rt9059gqw-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.02,+ 3,+ 0.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b19fbe55a90ae09a2e747407d6f7bfa9beb51451680d9a83e6552e53a4a0d102",+ "checked": "2026-10-17",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}
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rt9059gqw-hero.glbadded⋯ 1 unchanged line ⋯
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