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RT9040GQW
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Richtek Tech Linear Voltage Regulators (LDO), WDFN-10(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownRT9040GQW
Richtek Tech · Linear Voltage Regulators (LDO) · WDFN-10(3x3)
RT9040GQW from Richtek Tech, in a WDFN-10(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REFIN | input | Reference input that sets the regulated output voltage, with REFIN above 0.39V required for the regulator to be enabled. |
| 2 | VIN | power_in | Supply voltage for the LDO, specified at 1.1V to 3.5V. |
| 3 | VOUT | power_out | Power output of the LDO that feeds the DDR termination bus and needs at least 20µF of ceramic output capacitance. |
| 4 | PGND | power_in | Power ground return for the LDO output stage. |
| 5 | SENSE | input | Voltage sense input for the LDO, connected to the positive terminal of the output capacitor or the load. |
| 6 | REFOUT | power_out | Reference output that sources or sinks up to 10mA and should be bypassed to GND with a 0.1µF ceramic capacitor. |
| 7 | EN | input | Chip enable that is connected to SLP_S3 in DDR VTT applications and otherwise works as the ON/OFF function. |
| 8 | GND | power_in | Signal ground that connects to the negative terminal of the output capacitor. |
| 9 | PGOOD | output | Open-drain power good output that indicates whether the output is in regulation. |
| 10 | VCNTL | power_in | Supply input of 2.5V, 3.3V or 5V that requires a ceramic decoupling capacitor between 1µF and 4.7µF. |
| 11 | GND | power_in | Exposed pad that is the signal ground and must be soldered to a large PCB ground for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | WDFN-10(3x3) |
| Category | Power Management ICs |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCNTL Supply Current | IVCNTL | 0.9 | 2 | mA | VEN = 3.3V, No Load | 3 | |
| VCNTL Shutdown Current | ISHDN_VCNTL | 65 | 80 | A | VEN = 0V, VREFIN = 0, No Load | 3 | |
| VCNTL Shutdown Current | ISHDN_VCNTL | 200 | 500 | A | VEN = 0V, VREFIN > 0.4V, No Load | 3 | |
| VIN Supply Current | IVIN | 2 | mA | VEN = 3.3V, No Load | 3 | ||
| VIN Shutdown Current | ISHDN_VIN | 0.1 | 50 | A | VEN = 0V, No Load | 3 | |
| REFIN Input Current | IREFIN | 1 | A | VEN = 3.3 V | 3 | ||
| Offset Voltage of Output DC Voltage (DDRI) | VVOTOL | -10 | 10 | mV | VIN = 2.5 V, VREFOUT = 1.25 V (DDRI), IOUT = 0A | 3 | |
| Offset Voltage of Output DC Voltage (DDRII) | VVOTOL | -10 | 10 | mV | VIN = 1.8 V, VREFOUT = 0.9V (DDRII), IOUT = 0A | 3 | |
| Offset Voltage of Output DC Voltage (DDRIII) | VVOTOL | -10 | 10 | mV | VIN = 1.5 V, VREFOUT = 0.75V (DDRIII), IOUT = 0A | 3 | |
| VOUT Load Regulation | VLOAD | -15 | 15 | mV | -2A < IOUT < 2A | 3 | |
| Supply Input Voltage VCNTL | 2.375 | 5.5 | V | 3 | |||
| Supply Input Voltage VIN | 1.1 | 3.5 | V | 3 | |||
| Junction Temperature Range | -40 | 125 | °C | 3 | |||
| Ambient Temperature Range | -40 | 85 | °C | 3 | |||
| Supply Input Voltage VIN, REFIN, VCNTL | 6 | V | 3 | ||||
| Enable Voltage EN | 6 | V | 3 | ||||
| Power Dissipation PD @ TA = 25°C | PD | 1.429 | W | WDFN-10L 3x3, TA = 25°C | 3 | ||
| Package Thermal Resistance θJA | θJA | 70 | °C/W | WDFN-10L 3x3 | 3 | ||
| Package Thermal Resistance θJC | θJC | 8.2 | °C/W | WDFN-10L 3x3 | 3 | ||
| Lead Temperature (Soldering) | 260 | °C | 10 sec. | 3 | |||
| Junction Temperature | 150 | °C | 3 | ||||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| ESD HBM | 2 | kV | Human Body Model | 3 | |||
| ESD MM | 200 | V | Machine Model | 3 | |||
| VOUT Source Current Limit | ILIM_VOUT_sr | 3.5 | 5.5 | A | VCNTL = 5V (VOUT in PGOOD window) | 4 | |
| VOUT Sink Current Limit | ILIM_VOUT_sk | 3.5 | 5.5 | A | VCNTL = 5V (VOUT in PGOOD window) | 4 | |
| VOUT Discharge Resistance | RDISCHARGE | 18 | 25 | VREFIN = 0V, VOUT = 0.3V, VEN = 0V | 4 | ||
| VOUT PGOOD Threshold | VTH_PGOOD | 23.5 | 20 | 17.5 | % | PGOOD window lower threshold with respect to REFOUT | 4 |
| Output Low Voltage | VLOW_PGOOD | 0.4 | V | ISINK = 4mA | 4 | ||
| PGOOD Leakage Current | ILEAKAGE_PGOOD | 1 | A | VSENSE = VREFIN (PGOOD high impedance), PGOOD = VCNTL + 0.2 V | 4 | ||
| REFIN Voltage Range | VREFIN | 0.5 | 1.8 | V | 4 | ||
| REFIN Under Voltage Lockout | VUVLO_REFIN | 360 | 390 | 420 | mV | REFIN Rising | 4 |
| REFOUT Voltage Tolerance to VREFIN | VTOL_REFOUT | -15 | 15 | mV | 10mA < IREFOUT < 10mA, VREFIN = 1.25 V | 4 | |
| REFOUT Source Current Limit | ILIM_REFOUT_sr | 10 | 40 | mA | VREFOUT = 0V | 4 | |
| REFOUT Sink Current Limit | ILIM_REFOUT_sk | 10 | 40 | mA | VREFOUT = VIN | 4 | |
| UVLO Threshold | VUVLO_VCNTL | 2.2 | 2.3 | 2.375 | V | Wake up | 4 |
| High-Level Input Voltage | VIN_H | 1.7 | V | Enable | 4 | ||
| Low-Level Input Voltage | VIN_L | 0.3 | V | Enable | 4 | ||
| Logic Input Leakage Current | ILEAKAGE_EN | -1 | 1 | A | Enable | 4 |
CAD (KiCad official)
- Symbol:
RT9040GQW - Footprint:
Package_DFN_QFN:WDFN-10-1EP_3x3mm_P0.5mm_EP1.8x2.5mm - 3D model: WDFN-10(3x3) (KiCad packages3D, STEP)
- 3D model files:
rt9040gqw-etched.step/rt9040gqw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt9040gqw.step/rt9040gqw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (11 pp, sha256
13baae5203f359c6, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).