# RT8816AGQW

**Richtek Tech** · AC-DC Controllers And Regulators · QFN-20-EP(3x3)

RT8816AGQW from Richtek Tech, in a QFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT1 | power_out | Bootstrap supply for PWM1 that powers the high-side MOSFET driver. |
| 2 | UGATE1 | output | High-side gate driver output of PWM1 that connects to the gate of the converter's high-side MOSFET. |
| 3 | EN | input | Active-high enable control input; when PVCC powers on, the EN input voltage must not exceed PVCC. |
| 4 | PSI | input | Power-saving interface that selects the operating mode by voltage level: below 0.4V for 1-phase DEM, 0.7V to 0.88V for 1-phase forced CCM, 1.08V to 1.35V for 2-phase DEM, and 1.6V to 5.5V for 2-phase forced CCM. |
| 5 | VID | input | Programming input for output voltage control, referenced to the PWM-VID Dynamic Voltage Control section. |
| 6 | REFADJ | output | Reference adjustment output used in PWM-VID dynamic voltage control. |
| 7 | REFIN | input | External reference input. |
| 8 | VREF | power_in | High-precision 2V reference voltage output, referenced to RGND. |
| 9 | TON | input | On-time and switching-frequency adjustment input; an optional 100pF ceramic capacitor to ground may be added for noise immunity. |
| 10 | RGND | input | Negative remote sense input that connects to the ground of the output load. |
| 11 | VSNS | input | Positive remote sense input that connects to the positive terminal of the output load. |
| 12 | OCSET/SS | passive | Current-limit setting pin: a resistor to GND sets the current-limit threshold, and a capacitor to GND can set the external soft-start time. |
| 13 | PGOOD | output | Active-high open-drain power-good indicator output. |
| 14 | UGATE2 | output | High-side gate driver output of PWM2 that connects to the gate of the converter's high-side MOSFET. |
| 15 | BOOT2 | power_out | Bootstrap supply for PWM2 that powers the high-side MOSFET driver. |
| 16 | PHASE2 | passive | Switch node for PWM2 that returns the high-side driver current and connects to the high-side MOSFET source, low-side MOSFET drain, and inductor. |
| 17 | LGATE2 | output | Low-side gate driver output of PWM2 that connects to the gate of the converter's low-side MOSFET. |
| 18 | PVCC | power_in | Supply voltage input that connects to a 5V bias supply and needs a high-quality bypass capacitor to GND. |
| 19 | LGATE1 | output | Low-side gate driver output of PWM1 that connects to the gate of the converter's low-side MOSFET. |
| 20 | PHASE1 | passive | Switch node for PWM1 that returns the high-side driver current and connects to the high-side MOSFET source, low-side MOSFET drain, and inductor. |
| 21 | GND | power_in | Ground and exposed pad, which should be soldered to a large PCB area and connected to GND for maximum thermal dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | QFN-20-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 2.5 |  | 26 | V |  | 5 |
| Supply Voltage | PVCC | 4.5 |  | 5.5 | V |  | 5 |
| Junction Temperature Range | TJ | -10 |  | 105 | °C |  | 5 |
| TON to GND |  | -0.3 |  | 30 | V | DC | 5 |
| RGND to GND |  | -0.7 |  | 0.7 | V |  | 5 |
| BOOTx to PHASEx |  | -0.3 |  | 6 | V | DC | 5 |
| BOOTx to PHASEx |  | -5 |  | 7.5 | V | <100ns | 5 |
| BOOTx to GND |  | -0.3 |  | 36 | V | DC | 5 |
| BOOTx to GND |  | -5 |  | 42 | V | <100ns | 5 |
| PHASEx to GND |  | -5 |  | 30 | V | DC | 5 |
| PHASEx to GND |  | -10 |  | 42 | V | <100ns | 5 |
| UGATEx to GND |  | -5 |  | 36 | V | DC | 5 |
| UGATEx to GND |  | -10 |  | 42 | V | <100ns | 5 |
| UGATEx to PHASEx |  | -0.3 |  | 6 | V | DC | 5 |
| UGATEx to PHASEx |  | -5 |  | 7.5 | V | <100ns | 5 |
| LGATEx to GND |  | -0.3 |  | 6 | V | DC | 5 |
| LGATEx to GND |  | -5 |  | 7.5 | V | <100ns | 5 |
| Other Pins |  | -0.3 |  | 6.5 | V |  | 5 |
| Power Dissipation | PD |  |  | 2.67 | W | TA = 25°C, WQFN-20L 3x3 | 5 |
| Lead Temperature (Soldering) |  |  |  | 260 | °C | Soldering, 10 sec. | 5 |
| Junction Temperature | TJ |  |  | 150 | °C |  | 5 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 5 |
| ESD Susceptibility |  |  |  | 2 | kV | HBM (Human Body Model), Note 3 | 5 |
| PVCC Supply Voltage | VPVCC | 4.5 |  | 5.5 | V |  | 6 |
| PVCC Shutdown Current | ISHDN |  |  | 10 | µA | VEN = 0V | 6 |
| PVCC POR Threshold |  | 3.8 | 4.1 | 4.4 | V |  | 6 |
| Switching Frequency | fSW | 270 | 300 | 330 | kHz | RTON = 500k (Note 5) | 6 |
| EN Input Voltage Logic-High | VEN_H | 1.2 |  | 5.5 | V | Logic-High | 6 |
| EN Input Voltage Logic-Low | VEN_L |  |  | 0.55 | V | Logic-Low | 6 |
| Mode Decision 2 Phase CCM | VPSI | 1.6 | 1.8 | 5.5 | V | 2 Phase CCM | 6 |
| Mode Decision 2 Phase DEM | VPSI | 1.08 | 1.2 | 1.35 | V | 2 Phase DEM | 6 |
| Mode Decision 1 Phase CCM | VPSI | 0.7 | 0.8 | 0.88 | V | 1 Phase CCM | 6 |
| Mode Decision 1 Phase DEM | VPSI |  | 0 | 0.4 | V | 1 Phase DEM | 6 |
| PWM-VID Input Voltage Logic H | VPWM-VID_H | 1.2 |  |  | V | Logic H, PWM-VID input for 1.8V GPIO setting | 6 |
| PWM-VID Input Voltage Logic L | VPWM-VID_L |  |  | 0.6 | V | Logic L, PWM-VID input for 1.8V GPIO setting | 6 |
| PWM-VID Tri-state Voltage | VPWM-VID_Tri | 0.8 |  | 1 | V |  | 6 |
| Zero Current Crossing Threshold |  | 8 |  | 8 | mV |  | 6 |
| Current Limit Setting Current | IOCSET | 9 | 10 | 11 | µA | TA = TJ = 25C | 6 |
| Absolute Over-Voltage Protection Threshold | VOVP, Absolute | 1.9 | 2 | 2.1 | V | VREFIN ≤ 1.33V | 6 |
| Relative Over-Voltage Protection Threshold | VOVP, Relative | 145 | 150 | 155 | % | VREFIN > 1.33V | 6 |
| Relative Under-Voltage Protection Threshold | VUVP | 35 | 40 | 45 | % |  | 6 |
| Error Amplifier VSNS Error Comparator Threshold (Valley) |  | 11 | 6 | 1 | mV | VREFIN = 1V | 7 |
| Reference Voltage | VVREF | 1.98 | 2 | 2.02 | V | Sourcing current = 1mA, VID no switching | 7 |
| UGATE Driver Source Resistance | RUGATEsr |  | 2 | 4 | Ω | BOOTx, PHASEx forced to 5V | 7 |
| UGATE Driver Sink Resistance | RUGATEsk |  | 1 | 2 | Ω | BOOTx, PHASEx forced to 5V | 7 |
| LGATE Driver Source Resistance | RLGATEsr |  | 1.5 | 3 | Ω | LGATEx, high state | 7 |
| LGATE Driver Sink Resistance | RLGATEsk |  | 0.7 | 1.5 | Ω | LGATEx, low state | 7 |
| Package Thermal Resistance Junction-to-Ambient | θJA |  | 30 |  | °C/W | WQFN-20L 3x3; Note 2: natural convection, TA = 25°C, JEDEC 51-7 four-layer board | 5 |
| Package Thermal Resistance Junction-to-Case | θJC |  | 7.5 |  | °C/W | WQFN-20L 3x3; Note 2: measured at exposed pad | 5 |

## CAD (KiCad official)

- Symbol: `RT8816AGQW`
- Footprint: `Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm`
- 3D model: QFN-20-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `rt8816agqw-etched.step` / `rt8816agqw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt8816agqw.step` / `rt8816agqw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Richtek Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590234576083202048) (21 pp, sha256 `323f1534d015b905`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/rt8816agqw-datasheet.pdf)