component
RT8296AHZSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
rt8296ahzsp: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
7ab0667
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{
"schema_version": 1,
"type": "component",
"slug": "rt8296ahzsp",
"title": "RT8296AHZSP",
"brief": "Richtek Tech DC-DC Converters, SOP-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.2.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"pmic",
"rt8296ahzsp"
],
"component": {
"mpn": "RT8296AHZSP",
"manufacturer": "Richtek Tech",
"package": "SOP-8-EP",
"pin_count": 9,
"category": "PMIC",
"subcategory": "DC-DC Converters",
"datasheet": "https://datasheet.lcsc.com/datasheet/pdf/c4ff41fef057cfc6a1521d1e8dcd5045.pdf",
"parts": {
"symbol": "rt8296ahzsp.kicad_sym",
"footprint": "rt8296ahzsp.kicad_mod",
"model_3d": "rt8296ahzsp-etched.glb",
"model_3d_plain": "rt8296ahzsp.glb",
"model_3d_step": "rt8296ahzsp-etched.step",
"model_3d_step_plain": "rt8296ahzsp.step",
"lbr": "rt8296ahzsp.lbr"
},
"distributor_links": {
"lcsc": "C259730"
},
"pins": [
{
"number": "1",
"name": "BOOT",
"type": "passive",
"description": "Bootstrap for high-side gate driver. Connect a 0.1μF or greater ceramic capacitor from BOOT to SW to provide the boosted gate-drive voltage for the internal high-side N-MOSFET. Absolute max 31.3V; VBOOT − VSW max 6V."
},
{
"number": "2",
"name": "VIN",
"type": "power_in",
"description": "Input supply voltage, 4.5V to 23V operating range (absolute max 25V). Must be bypassed with a suitably large ceramic capacitor (e.g. 10μF x 2) placed close to the pin."
},
{
"number": "3",
"name": "SW",
"type": "power_out",
"description": "Switch (phase) node. Connect to the external L-C output filter. This is the drain node of the internal high-side and source of the internal low-side N-MOSFETs (RDS(ON) ≈ 85mΩ each), swinging between GND and VIN at 340kHz."
},
{
"number": "4",
"name": "GND",
"type": "power_in",
"description": "Ground return. Pin 4 and the exposed pad (pin 9) must both be tied to ground; solder the exposed pad to a large PCB copper area for maximum power dissipation (θJA = 75°C/W, θJC = 15°C/W)."
},
{
"number": "5",
"name": "FB",
"type": "input",
"description": "Feedback input. Regulates to an internal 0.8V (±1.5%) reference. For adjustable output, connect an external resistive divider from VOUT to FB to GND to set the output voltage from 0.8V to 20V."
},
{
"number": "6",
"name": "COMP",
"type": "output",
"description": "Error-amplifier compensation node (GEA ≈ 940μA/V). Connect a series RC network from COMP to GND to compensate the current-mode control loop; an optional capacitor from COMP to GND may be added for a high-frequency pole."
},
{
"number": "7",
"name": "EN",
"type": "input",
"description": "Enable input. Logic-high (VIH ≥ 2.7V) enables the converter; logic-low (VIL ≤ 0.4V) forces shutdown, reducing supply current to <3μA. Tie to VIN through a 100kΩ pull-up for automatic startup. Absolute max 6V."
},
{
"number": "8",
"name": "SS",
"type": "passive",
"description": "Soft-start control input. Connect a capacitor from SS to GND to program the soft-start ramp period; ISS ≈ 6μA charging current. A 0.1μF capacitor sets tSS ≈ 13.5ms."
},
{
"number": "9",
"name": "GND (Exposed Pad)",
"type": "power_in",
"description": "Exposed thermal pad on the bottom of the SOP-8 package. Must be soldered to a large PCB ground plane and electrically connected to GND for proper operation and maximum power dissipation."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://datasheet.lcsc.com/datasheet/pdf/c4ff41fef057cfc6a1521d1e8dcd5045.pdf",
"pages": 14,
"sha256": "65b4ec20534cc22d",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 9,
"described": 9,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"pin1": {
"pad": "1",
"at": [
-2.475,
-1.905
],
"corner": "top-left",
"source": "silk-marker",
"derived_from": "SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm@sha256:a7971720bdda0353",
"mark": "drawn"
},
"models_3d": [
{
"file": "rt8296ahzsp.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.55
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "2d6f7e774e8143e3320cbd59eb5be9f3b7864614644e3b072006e1eb05fb7fa6",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "rt8296ahzsp-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.55
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "44e3ab959a45e578025a6a0a3a07227607f4ebdd74484081240afb45ca501387",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Richtek Tech",
"Package": "SOP-8-EP",
"Category": "PMIC",
"Pins": "9"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"rt8296ahzsp"
],
"discovery_pitch": "RT8296AHZSP (Richtek Tech) component page with datasheet-verified CAD.",
"author": {
"name": "Ray"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"rt8296ahzsp.kicad_sym",
"rt8296ahzsp.kicad_mod",
"rt8296ahzsp.glb",
"rt8296ahzsp.step",
"rt8296ahzsp-etched.step",
"rt8296ahzsp.lbr",
"docs/hero.png",
"docs/rt8296ahzsp-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html"
],
"variants": [
{
"mpn": "RT8296AHZSP",
"kind": "packaging"
},
{
"mpn": "RT8296AHZSPLZSP",
"kind": "packaging"
},
{
"mpn": "RT8296AHZSPHGSP",
"kind": "packaging"
},
{
"mpn": "RT8296AHZSPLGSP",
"kind": "packaging"
}
],
"updated_at": "2026-09-25T05:16:20.317Z"
}