component
RT8295BHZSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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RT8295BHZSP
Richtek Tech · DC-DC Converters · SOP-8-EP
RT8295BHZSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap for the high-side gate driver; connect a 0.1μF or greater ceramic capacitor from BOOT to SW. |
| 2 | VIN | power_in | Input supply voltage, 4.5V to 23V; must be bypassed with a suitably large ceramic capacitor. |
| 3 | SW | output | Switch node; connect this pin to an external L-C filter. |
| 4 | GND | power_in | Ground; the exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. |
| 5 | FB | input | Feedback input connected to the converter output, regulating to the internal 0.8V typical reference through an internal divider or an external resistive divider for adjustable output. |
| 6 | COMP | passive | Compensation node for the control loop; connect a series RC network from COMP to GND, with an additional capacitor from COMP to GND sometimes required. |
| 7 | EN | input | Chip enable, active high; a logic-low (<0.4V) forces shutdown with supply current below 3μA, and a 100kΩ pull-up from VIN gives automatic startup. |
| 8 | SS | passive | Soft-start control; a capacitor from SS to GND sets the soft-start period, with 0.1μF giving 13.5ms typical. |
| 9 | GND | power_in | Exposed thermal pad on the package bottom, which must be soldered to a large PCB copper area and connected to GND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown Supply Current | 0.5 | 3 | μA | VEN = 0V | 4 | ||
| Supply Current | 0.8 | 1.2 | mA | VEN = 3 V, VFB = 0.9V | 4 | ||
| Feedback Voltage | VFB | 0.788 | 0.8 | 0.812 | V | 4.5V ≤ VIN ≤ 23V | 4 |
| High Side Switch Leakage Current | 0 | 10 | μA | VEN = 0V, VSW = 0V | 4 | ||
| Oscillation Frequency | fOSC1 | 1 | 1.2 | 1.4 | MHz | 4 | |
| EN Input Threshold Logic-High Voltage | VIH | 2.7 | 5.5 | V | 5 | ||
| EN Input Threshold Logic-Low Voltage | VIL | 0.4 | V | 5 | |||
| Input Under Voltage Lockout Threshold | VUVLO | 3.8 | 4.2 | 4.5 | V | VIN Rising | 5 |
| Supply Voltage | VIN | 4.5 | 23 | V | 4 | ||
| Junction Temperature Range | -40 | 125 | °C | 4 | |||
| Ambient Temperature Range | -40 | 85 | °C | 4 | |||
| Supply Voltage | VIN | -0.3 | 25 | V | 4 | ||
| Input Voltage SW | VSW | -0.3 | V | Upper limit printed as (VIN + 0.3V) | 4 | ||
| VBOOT − VSW | VBOOT−VSW | -0.3 | 6 | V | 4 | ||
| Other Pin Voltages | -0.3 | 6 | V | 4 | |||
| Power Dissipation SOP-8 (Exposed Pad) | PD | 1.333 | W | TA = 25°C | 4 | ||
| Package Thermal Resistance Junction-to-Ambient SOP-8 (Exposed Pad) | θJA | 75 | °C/W | JEDEC 51-7 four-layer board, natural convection, TA = 25°C | 4 | ||
| Package Thermal Resistance Junction-to-Case SOP-8 (Exposed Pad) | θJC | 15 | °C/W | Measured on the exposed pad of the package | 4 | ||
| Lead Temperature (Soldering) | 260 | °C | 10 sec | 4 | |||
| Junction Temperature | 150 | °C | 4 | ||||
| Storage Temperature Range | -65 | 150 | °C | 4 | |||
| ESD Susceptibility HBM | 2 | kV | Human Body Model | 4 | |||
| ESD Susceptibility MM | 200 | V | Machine Model | 4 |
CAD (KiCad official)
- Symbol:
RT8295BHZSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
rt8295bhzsp-etched.step/rt8295bhzsp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt8295bhzsp.step/rt8295bhzsp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (14 pp, sha256
8419f309725511ed, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# RT8295BHZSP
**Richtek Tech** · DC-DC Converters · SOP-8-EP
RT8295BHZSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap for the high-side gate driver; connect a 0.1μF or greater ceramic capacitor from BOOT to SW. |
| 2 | VIN | power_in | Input supply voltage, 4.5V to 23V; must be bypassed with a suitably large ceramic capacitor. |
| 3 | SW | output | Switch node; connect this pin to an external L-C filter. |
| 4 | GND | power_in | Ground; the exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. |
| 5 | FB | input | Feedback input connected to the converter output, regulating to the internal 0.8V typical reference through an internal divider or an external resistive divider for adjustable output. |
| 6 | COMP | passive | Compensation node for the control loop; connect a series RC network from COMP to GND, with an additional capacitor from COMP to GND sometimes required. |
| 7 | EN | input | Chip enable, active high; a logic-low (<0.4V) forces shutdown with supply current below 3μA, and a 100kΩ pull-up from VIN gives automatic startup. |
| 8 | SS | passive | Soft-start control; a capacitor from SS to GND sets the soft-start period, with 0.1μF giving 13.5ms typical. |
| 9 | GND | power_in | Exposed thermal pad on the package bottom, which must be soldered to a large PCB copper area and connected to GND for maximum power dissipation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown Supply Current | | | 0.5 | 3 | μA | VEN = 0V | 4 |
| Supply Current | | | 0.8 | 1.2 | mA | VEN = 3 V, VFB = 0.9V | 4 |
| Feedback Voltage | VFB | 0.788 | 0.8 | 0.812 | V | 4.5V ≤ VIN ≤ 23V | 4 |
| High Side Switch Leakage Current | | | 0 | 10 | μA | VEN = 0V, VSW = 0V | 4 |
| Oscillation Frequency | fOSC1 | 1 | 1.2 | 1.4 | MHz | | 4 |
| EN Input Threshold Logic-High Voltage | VIH | 2.7 | | 5.5 | V | | 5 |
| EN Input Threshold Logic-Low Voltage | VIL | | | 0.4 | V | | 5 |
| Input Under Voltage Lockout Threshold | VUVLO | 3.8 | 4.2 | 4.5 | V | VIN Rising | 5 |
| Supply Voltage | VIN | 4.5 | | 23 | V | | 4 |
| Junction Temperature Range | | -40 | | 125 | °C | | 4 |
| Ambient Temperature Range | | -40 | | 85 | °C | | 4 |
| Supply Voltage | VIN | -0.3 | | 25 | V | | 4 |
| Input Voltage SW | VSW | -0.3 | | | V | Upper limit printed as (VIN + 0.3V) | 4 |
| VBOOT − VSW | VBOOT−VSW | -0.3 | | 6 | V | | 4 |
| Other Pin Voltages | | -0.3 | | 6 | V | | 4 |
| Power Dissipation SOP-8 (Exposed Pad) | PD | | 1.333 | | W | TA = 25°C | 4 |
| Package Thermal Resistance Junction-to-Ambient SOP-8 (Exposed Pad) | θJA | | 75 | | °C/W | JEDEC 51-7 four-layer board, natural convection, TA = 25°C | 4 |
| Package Thermal Resistance Junction-to-Case SOP-8 (Exposed Pad) | θJC | | 15 | | °C/W | Measured on the exposed pad of the package | 4 |
| Lead Temperature (Soldering) | | | | 260 | °C | 10 sec | 4 |
| Junction Temperature | | | | 150 | °C | | 4 |
| Storage Temperature Range | | -65 | | 150 | °C | | 4 |
| ESD Susceptibility HBM | | | | 2 | kV | Human Body Model | 4 |
| ESD Susceptibility MM | | | | 200 | V | Machine Model | 4 |
## CAD (KiCad official)
- Symbol: `RT8295BHZSP`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `rt8295bhzsp-etched.step` / `rt8295bhzsp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt8295bhzsp.step` / `rt8295bhzsp.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Richtek Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884623275266048) (14 pp, sha256 `8419f309725511ed`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/rt8295bhzsp-datasheet.pdf)