component
RT8290ZSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 13d ago |
| viewers | 13d ago |
| package.json | 13d ago |
| page.json | 13d ago |
| README.md | 13d ago |
| rt8290zsp-etched.glb | 13d ago |
| rt8290zsp-etched.step | 13d ago |
| rt8290zsp-hero.glb | 13d ago |
| rt8290zsp-hero.overlay.json | 13d ago |
| rt8290zsp.glb | 13d ago |
| rt8290zsp.kicad_mod | 13d ago |
| rt8290zsp.kicad_sym | 13d ago |
| rt8290zsp.lbr | 13d ago |
| rt8290zsp.step | 13d ago |
RT8290ZSP
Richtek Tech · DC-DC Converters · SOP-8-EP
RT8290ZSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_out | Bootstrap supply for the high-side gate driver; connect a 10nF or greater ceramic capacitor from BOOT to SW. |
| 2 | VIN | power_in | Voltage supply input with a range of 4.5V to 23V; a suitably large capacitor must be bypassed with this pin. |
| 3 | SW | output | Switching node; connect the output LC filter between SW and the output load. |
| 4 | GND | power_in | Ground; connect to the exposed pad and a large PCB ground for maximum power dissipation. |
| 5 | FB | input | Output voltage feedback input with a 0.925V typical reference (0.911V to 0.939V over 4.5V to 23V VIN). |
| 6 | COMP | passive | Loop compensation node; a series RC network is required from COMP to GND, with an optional additional capacitor from COMP to GND. |
| 7 | EN | input | Enable input: logic high enables the converter, logic low forces shutdown with supply current below 3µA; tie to VIN through a 100k pull-up for automatic startup. |
| 8 | SS | passive | Soft-start control; a capacitor from SS to GND sets the soft-start period, with 0.1µF giving 15.5ms typical. |
| 9 | GND | power_in | Exposed thermal pad that must be soldered to a large PCB and connected to GND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VIN | -0.3 | 25 | V | 3 | ||
| Switching Voltage | SW | -0.3 | V | max printed as (VIN + 0.3V) | 3 | ||
| SW (AC) 30ns | SW | -5 | 30 | V | 30ns | 3 | |
| The Other Pins | -0.3 | 6 | V | 3 | |||
| Power Dissipation | PD | 1.333 | W | TA = 25°C, SOP-8 (Exposed Pad) | 3 | ||
| Junction Temperature | 150 | °C | 3 | ||||
| Lead Temperature | 260 | °C | soldering, 10 sec | 3 | |||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| ESD Susceptibility HBM | 2 | kV | Human Body Model | 3 | |||
| ESD Susceptibility MM | 200 | V | Machine Model | 3 | |||
| Supply Voltage | VIN | 4.5 | 23 | V | 3 | ||
| Enable Voltage | VEN | 0 | 5.5 | V | 3 | ||
| Junction Temperature Range | -40 | 125 | °C | 3 | |||
| Ambient Temperature Range | -40 | 85 | °C | 3 | |||
| Junction to Ambient Thermal Resistance | θJA | 75 | °C/W | TA = 25°C, four-layer JEDEC 51-7 board | 3 | ||
| Junction to Case Thermal Resistance | θJC | 15 | °C/W | measured at exposed pad | 3 | ||
| Shutdown Supply Current | 0.3 | 3 | A | VEN = 0V | 4 | ||
| Supply Current | 0.8 | 1.2 | mA | VEN = 3V, VFB = 1V | 4 | ||
| Feedback Voltage | VFB | 0.911 | 0.925 | 0.939 | V | 4.5V ≤ VIN ≤ 23V | 4 |
| High Side Switch Leakage Current | 0 | 10 | A | VEN = 0V, VSW = 0V | 4 | ||
| Oscillation Frequency | fOSC1 | 300 | 340 | 380 | kHz | 4 | |
| EN Input Threshold Logic-High Voltage | VIH | 2.7 | V | 4 | |||
| EN Input Threshold Logic-Low Voltage | VIL | 0.4 | V | 4 | |||
| Input Under Voltage Lockout Threshold | VUVLO | 3.8 | 4.2 | 4.5 | V | VIN Rising | 4 |
CAD (KiCad official)
- Symbol:
RT8290ZSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
rt8290zsp-etched.step/rt8290zsp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt8290zsp.step/rt8290zsp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (12 pp, sha256
86e7690908efc448, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).