component
RT8251GSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 14d ago |
| viewers | 14d ago |
| package.json | 14d ago |
| page.json | 14d ago |
| README.md | 14d ago |
| rt8251gsp-etched.glb | 14d ago |
| rt8251gsp-etched.step | 14d ago |
| rt8251gsp-hero.glb | 14d ago |
| rt8251gsp-hero.overlay.json | 14d ago |
| rt8251gsp.glb | 14d ago |
| rt8251gsp.kicad_mod | 14d ago |
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| rt8251gsp.step | 14d ago |
RT8251GSP
Richtek Tech · DC-DC Converters · SOP-8-EP
RT8251GSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap pin: a 100nF low-ESR capacitor between BOOT and SW forms a floating supply that drives the high-side gate, at about 5V across it. |
| 2 | VIN | power_in | Power input supplying the IC and the step-down switches; connect to a 4.75V to 24V source with enough capacitance to GND to eliminate input noise. |
| 3 | SW | power_out | Power switching output that connects the output LC filter to the load; a capacitor is required from SW to BOOT to power the high-side switch. |
| 4 | GND | power_in | Ground and voltage reference for the regulated output, to be routed outside the D1-to-CIN ground path to keep switching spikes out of the reference. |
| 5 | FB | input | Feedback input; an external resistor divider from the output to GND sets the output voltage against the 0.8V typical reference (0.784V to 0.816V). |
| 6 | COMP | passive | Output of the transconductance error amplifier and input to the current comparator; frequency compensation is done with a series R-C to ground. |
| 7 | EN | input | Enable input: drive above 1.4V to turn the regulator on and below 0.4V to turn it off; leave unconnected for automatic startup. |
| 8 | SS | passive | Soft-start control input; connect a capacitor of at least 10nF from SS to GND, where 10nF sets a 1ms soft-start period. |
| 9 | GND | power_in | Exposed thermal pad that must be soldered to a large PCB copper area and connected to GND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (absolute maximum) | VIN | -0.3 | 26 | V | 4 | ||
| Switching Voltage (absolute maximum) | VSW | -0.3 | V | Upper limit printed as VIN + 0.3V | 4 | ||
| BOOT Voltage (absolute maximum) | VBOOT | -0.3 | 6 | V | Referenced to VSW: (VSW − 0.3V) to (VSW + 6V) | 4 | |
| All Other Pins (absolute maximum) | -0.3 | 6 | V | 4 | |||
| Power Dissipation, SOP-8 (Exposed Pad) | PD | 1.333 | W | TA = 25°C | 4 | ||
| Enable Voltage | VEN | 0 | 5.5 | V | 4 | ||
| Supply Voltage (recommended) | VIN | 4.75 | 24 | V | 4 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 4 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 4 | ||
| Feedback Reference Voltage | VFB | 0.784 | 0.8 | 0.816 | V | 4.75V ≦ VIN ≦ 24V | 5 |
| High-Side Switch Leakage Current | 10 | μA | VEN = 0V, VSW = 0V | 5 | |||
| Oscillator Frequency | fSW | 420 | 570 | 720 | kHz | 5 | |
| Logic Low (EN) | VIL | 0.4 | V | 5 | |||
| EN Input Voltage Logic High | VIH | 1.4 | 5.5 | V | 5 | ||
| Quiescent Current | IQ | 0.8 | 1 | mA | VEN = 2V, VFB = 1V | 5 | |
| High-Side Switch-On Resistance | RDS(ON)1 | 70 | mΩ | 5 | |||
| Low-Side Switch-On Resistance | RDS(ON)2 | 15 | Ω | 5 | |||
| Current Limit | ILIM | 6.8 | A | Duty = 85%; VBOOT−SW = 4.8V | 5 | ||
| Current Sense Transconductance | GCS | 4.6 | A/V | Output Current to VCOMP | 5 | ||
| Error Amplifier Transconductance | gm | 920 | μA/V | ΔIC = ±10μA | 5 | ||
| Short Circuit Oscillation Frequency | 185 | kHz | VFB = 0V | 5 | |||
| Maximum Duty Cycle | DMAX | 85 | % | VFB = 0.7V | 5 | ||
| Minimum On-Time | tON | 100 | ns | 5 | |||
| UVLO Threshold Rising | 4.1 | V | 5 | ||||
| UVLO Threshold Hysteresis | 200 | mV | 5 | ||||
| Enable Pull Up Current | 1 | μA | VEN = 0V | 5 | |||
| Shutdown Current | ISHDN | 25 | μA | VEN = 0V | 5 | ||
| Soft-Start Current | ISS | 10 | μA | VSS = 0V | 5 | ||
| Soft-Start Period | 1 | ms | CSS = 10nF | 5 | |||
| Thermal Shutdown | TSD | 150 | °C | 5 | |||
| Junction Temperature (absolute maximum) | TJ | 150 | °C | 4 | |||
| Lead Temperature (soldering) | 260 | °C | Soldering, 10 sec | 4 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 4 | ||
| ESD Susceptibility HBM | 2 | kV | Human Body Model | 4 | |||
| Package Thermal Resistance, Junction-to-Ambient, SOP-8 (Exposed Pad) | θJA | 75 | °C/W | Minimum copper area layout, JEDEC 51-7 four-layer board | 4 | ||
| Package Thermal Resistance, Junction-to-Case, SOP-8 (Exposed Pad) | θJC | 15 | °C/W | Measured at the exposed pad | 4 |
CAD (KiCad official)
- Symbol:
RT8251GSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
rt8251gsp-etched.step/rt8251gsp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt8251gsp.step/rt8251gsp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (16 pp, sha256
1c0ef95bca25caf6, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).