component
RT8250NGSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 12d ago |
| viewers | 12d ago |
| package.json | 12d ago |
| page.json | 12d ago |
| README.md | 12d ago |
| rt8250ngsp-etched.glb | 12d ago |
| rt8250ngsp-etched.step | 12d ago |
| rt8250ngsp-hero.glb | 12d ago |
| rt8250ngsp-hero.overlay.json | 12d ago |
| rt8250ngsp.glb | 12d ago |
| rt8250ngsp.kicad_mod | 12d ago |
| rt8250ngsp.kicad_sym | 12d ago |
| rt8250ngsp.lbr | 12d ago |
| rt8250ngsp.step | 12d ago |
RT8250NGSP
Richtek Tech · DC-DC Converters · SOIC-8-EP
RT8250NGSP from Richtek Tech, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap for the high-side gate driver; connect a 10nF or greater ceramic capacitor from BOOT to SW (BOOT voltage range is VSW − 0.3V to VSW + 6V). |
| 2 | VIN | power_in | Voltage supply input with a range of 4.75V to 23V (absolute maximum 24V), which must be bypassed with a suitably large capacitor. |
| 3 | SW | power_out | Switching node to which the output LC filter is connected between the SW pin and the output load (−0.3V to VIN + 0.3V). |
| 4 | GND | power_in | Ground pin, which is connected to GND together with the exposed pad (pin 9) for maximum power dissipation. |
| 5 | FB | input | Output voltage feedback input with a typical feedback reference voltage of 0.925V. |
| 6 | COMP | passive | Compensation node for the regulation control loop, requiring a series RC network from COMP to GND and optionally an additional capacitor to GND. |
| 7 | EN | input | Enable input where logic high enables the converter and logic low forces shutdown with supply current below 3μA (VIH min 2.7V, VIL max 0.4V; recommended 0V to 5.5V). |
| 8 | SS | passive | Soft-start control input where a capacitor to GND sets the soft-start period, with 0.1μF giving 13ms typically from a 7μA charge current. |
| 9 | GND | power_in | Exposed pad that must be soldered to a large PCB and connected to GND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOIC-8-EP |
| Category | Power Management ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown Supply Current | 0.3 | 3 | μA | VEN = 0V | 4 | ||
| Supply Current | 0.7 | 1.2 | mA | VEN = 3 V, VFB = 1.0V | 4 | ||
| Feedback Voltage | VFB | 0.9 | 0.925 | 0.95 | V | 4.75V ≤ VIN ≤ 23V | 4 |
| High-Side Switch Leakage Current | 0 | 10 | μA | VEN = 0V, VSW = 0V | 4 | ||
| Oscillation Frequency | fOSC1 | 300 | 340 | 380 | kHz | 4 | |
| EN Logic-High Voltage | VIH | 2.7 | V | 4 | |||
| EN Logic-Low Voltage | VIL | 0.4 | V | 4 | |||
| Input Under Voltage Lockout Threshold | 3.8 | 4.2 | 4.5 | V | VIN Rising | 4 | |
| Error Amplifier Transconductance | GEA | 1250 | μA/V | ΔIC = ±10μA | 4 | ||
| High-Side Switch On-Resistance | RDS(ON)1 | 100 | mΩ | 4 | |||
| Low-Side Switch On-Resistance | RDS(ON)2 | 85 | mΩ | 4 | |||
| Thermal Shutdown | TSD | 150 | °C | 4 | |||
| Supply Voltage (recommended) | VIN | 4.75 | 23 | V | 3 | ||
| Enable Voltage (recommended) | VEN | 0 | 5.5 | V | 3 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 3 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 3 | ||
| Supply Voltage | VIN | -0.3 | 24 | V | 3 | ||
| BOOT Voltage | -0.3 | 6 | V | (VSW − 0.3V) to (VSW + 6V) | 3 | ||
| The Other Pins | -0.3 | 6 | V | 3 | |||
| Power Dissipation | PD | 1.333 | W | TA = 25°C, SOP-8 (Exposed Pad) | 3 | ||
| Junction Temperature | TJ | 150 | °C | 3 | |||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 3 | |||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| ESD HBM | 2 | kV | Human Body Mode | 3 | |||
| ESD MM | 200 | V | Machine Mode | 3 | |||
| Thermal Resistance Junction to Ambient | θJA | 75 | °C/W | SOP-8 (Exposed Pad) | 3 | ||
| Thermal Resistance Junction to Case | θJC | 15 | °C/W | SOP-8 (Exposed Pad) | 3 |
CAD (KiCad official)
- Symbol:
RT8250NGSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
rt8250ngsp-etched.step/rt8250ngsp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt8250ngsp.step/rt8250ngsp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (12 pp, sha256
63313b5d7aff591b, retrieved 2026-10-26, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).