component
RT8129AGQW
Public Made by Adomby adom
Richtek Tech DC-DC Controllers, TDFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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RT8129AGQW
Richtek Tech · DC-DC Controllers · TDFN-10-EP(3x3)
RT8129AGQW from Richtek Tech, in a TDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_in | Bootstrap supply for the high-side gate driver, connected to VCC through a bootstrap diode with a 0.1µF or greater ceramic capacitor to PHASE. |
| 2 | PHASE | passive | Switch node connected to the high-side MOSFET source, low-side MOSFET drain and inductor, sensed for zero-current detection and over-current protection while the low-side MOSFET is on. |
| 3 | UGATE | output | High-side MOSFET gate driver output, connected to the gate of the high-side MOSFET. |
| 4 | LGATE/OCSET | bidirectional | Low-side MOSFET gate driver output that also sets the current limit threshold through a resistor (ROCSET) to GND. |
| 5 | GND | power_in | Ground; pin 5 is tied to the exposed pad, which must be soldered to a large PCB ground area for maximum power dissipation. |
| 6 | VCC | power_in | Supply voltage input (4.5V to 13.2V recommended) that also powers the low-side gate driver, with a 4.7µF ceramic capacitor to GND recommended. |
| 7 | EN | input | Enable control input: above 2V turns the controller on, below 0.8V turns it off, and it is pulled high internally if left open. |
| 8 | FB | input | Output voltage feedback input, also monitored for power good, over-voltage and under-voltage protection, connected to the output through a resistor divider. |
| 9 | NC | unconnected | No internal connection. |
| 10 | PGOOD | output | Open-drain power good output requiring a pull-up resistor, high when the output is in regulation, and may be left open if unused. |
| 11 | GND | power_in | Exposed pad ground, to be soldered to a large PCB ground area for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | TDFN-10-EP(3x3) |
| Category | Power Supply Chip |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC POR Threshold (rising) | 4.4 | V | VCC rising | 6 | |||
| VCC POR Threshold (falling) | 3.9 | V | VCC falling | 6 | |||
| FB Error Comparator Threshold tolerance | -1 | 1 | % | Reference and Error Amplifier Excluding External Resistive Divider Tolerance | 6 | ||
| Output Voltage Range | 0.8 | 3.3 | V | 6 | |||
| PWM Frequency | FSW | 270 | 300 | 330 | kHz | Note 5 | 6 |
| EN Internal Pull High Current | 10 | 40 | A | VEN = 0V | 6 | ||
| EN Logic-High Input Voltage | VENH | 2 | V | 6 | |||
| EN Logic-Low Input Voltage | VENL | 0.8 | V | 6 | |||
| Over-Voltage Until PGOOD Goes Low | 880 | 902 | mV | Measured at FB, with respect to reference, no load | 6 | ||
| PGOOD Output Low Voltage | 0.4 | V | ISINK = 1mA | 6 | |||
| PGOOD Leakage Current | ILEAK | 1 | A | High state, forced to 5V | 6 | ||
| UGATE Gate Driver Source | RUGATEsr | 1.5 | 3 | Ω | VBOOT − VPHASE = 12V, ISOURCE = 100mA | 6 | |
| UGATE Gate Driver Sink | RUGATEsk | 2.25 | 4 | Ω | VBOOT − VPHASE = 12V, ISINK = 10mA | 6 | |
| LGATE Gate Driver Source | RLGATEsr | 1.5 | 3 | Ω | VCC = 12V, ISOURCE = 100mA | 6 | |
| LGATE Gate Driver Sink | RLGATEsk | 1 | 2 | Ω | VCC = 12V, ISOURCE = 10mA | 6 | |
| Dead Time (UG falling to LG rising) | 5 | 20 | ns | From UG falling to LG rising, PHASE = 1.5V | 6 | ||
| Dead Time (LG falling to UG rising) | 5 | 20 | ns | From LG falling to UG rising | 6 | ||
| Internal Boot Charging Switch on Resistance | 80 | Ω | VCC to BOOT, 10mA | 6 | |||
| Current Limit Setting Current | IOCSET | 9.5 | 10 | 10.5 | µA | 7 | |
| Current Limit Threshold Offset | -20 | 20 | mV | 7 | |||
| Over Voltage Protection Threshold | VOVP | 0.95 | 1 | 1.03 | V | 7 | |
| Under Voltage Protection Threshold | VUVP | 0.57 | 0.6 | 0.63 | V | 7 | |
| Voltage Ramp Soft-Start Time | 1.2 | 2 | 2.8 | ms | From FB 0% to FB 100% | 7 | |
| Thermal Shutdown Threshold | TSD | 145 | 165 | °C | 7 | ||
| Reference Voltage | VREF | 0.8 | V | 6 | |||
| Minimum On-Time | TON(MIN) | 70 | ns | 6 | |||
| Minimum Off-Time | TOFF(MIN) | 300 | ns | 6 | |||
| Under-Voltage Until PGOOD Goes Low | 720 | mV | Measured at FB, with respect to reference, no load | 6 | |||
| Fault Propagation Delay | 1 | µs | Falling edge, FB forced below PGOOD trip threshold | 6 | |||
| OVP latch delay | 5 | µs | 7 | ||||
| Power Input Voltage | VIN | 2.5 | 25 | V | 5 | ||
| Control Voltage | VCC | 4.5 | 13.2 | V | 5 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 5 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 5 | ||
| VCC to GND | VCC | -0.3 | 15 | V | 5 | ||
| Other Pins | -0.3 | 6.5 | V | 5 | |||
| BOOT to PHASE DC | -0.3 | 15 | V | DC | 5 | ||
| BOOT to PHASE | -0.3 | 20 | V | <100ns | 5 | ||
| PHASE to GND DC | -5 | 25 | V | DC | 5 | ||
| PHASE to GND | -10 | 30 | V | <100ns | 5 | ||
| BOOT to GND DC | -0.3 | 40 | V | DC | 5 | ||
| BOOT to GND | -0.3 | 45 | V | <100ns | 5 | ||
| UGATE to GND DC | -0.3 | 40 | V | DC | 5 | ||
| UGATE to GND | -10 | 45 | V | <100ns | 5 | ||
| UGATE to PHASE DC | -0.3 | 15 | V | DC | 5 | ||
| UGATE to PHASE | -5 | 20 | V | <40ns | 5 | ||
| LGATE to GND DC | -0.3 | 15 | V | DC | 5 | ||
| LGATE to GND | -5 | 20 | V | <100ns | 5 | ||
| Power Dissipation | PD | 3.27 | W | TA = 25C, WDFN-10L 3x3 | 5 | ||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 5 | |||
| Junction Temperature | TJ | 150 | °C | 5 | |||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| ESD Susceptibility HBM | 2 | kV | HBM (Human Body Model) | 5 | |||
| Thermal Resistance Junction to Ambient | θJA | 30.5 | °C/W | WDFN-10L 3x3, JEDEC 51-7 four-layer board | 5 | ||
| Thermal Resistance Junction to Case | θJC | 7.5 | °C/W | WDFN-10L 3x3, at exposed pad | 5 |
CAD (KiCad official)
- Symbol:
RT8129AGQW - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: TDFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
rt8129agqw-etched.step/rt8129agqw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt8129agqw.step/rt8129agqw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (18 pp, sha256
18c827b01f6fdd16, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# RT8129AGQW
**Richtek Tech** · DC-DC Controllers · TDFN-10-EP(3x3)
RT8129AGQW from Richtek Tech, in a TDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_in | Bootstrap supply for the high-side gate driver, connected to VCC through a bootstrap diode with a 0.1µF or greater ceramic capacitor to PHASE. |
| 2 | PHASE | passive | Switch node connected to the high-side MOSFET source, low-side MOSFET drain and inductor, sensed for zero-current detection and over-current protection while the low-side MOSFET is on. |
| 3 | UGATE | output | High-side MOSFET gate driver output, connected to the gate of the high-side MOSFET. |
| 4 | LGATE/OCSET | bidirectional | Low-side MOSFET gate driver output that also sets the current limit threshold through a resistor (ROCSET) to GND. |
| 5 | GND | power_in | Ground; pin 5 is tied to the exposed pad, which must be soldered to a large PCB ground area for maximum power dissipation. |
| 6 | VCC | power_in | Supply voltage input (4.5V to 13.2V recommended) that also powers the low-side gate driver, with a 4.7µF ceramic capacitor to GND recommended. |
| 7 | EN | input | Enable control input: above 2V turns the controller on, below 0.8V turns it off, and it is pulled high internally if left open. |
| 8 | FB | input | Output voltage feedback input, also monitored for power good, over-voltage and under-voltage protection, connected to the output through a resistor divider. |
| 9 | NC | unconnected | No internal connection. |
| 10 | PGOOD | output | Open-drain power good output requiring a pull-up resistor, high when the output is in regulation, and may be left open if unused. |
| 11 | GND | power_in | Exposed pad ground, to be soldered to a large PCB ground area for maximum power dissipation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | TDFN-10-EP(3x3) |
| Category | Power Supply Chip |
| Pins | 11 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC POR Threshold (rising) | | | | 4.4 | V | VCC rising | 6 |
| VCC POR Threshold (falling) | | 3.9 | | | V | VCC falling | 6 |
| FB Error Comparator Threshold tolerance | | -1 | | 1 | % | Reference and Error Amplifier Excluding External Resistive Divider Tolerance | 6 |
| Output Voltage Range | | 0.8 | | 3.3 | V | | 6 |
| PWM Frequency | FSW | 270 | 300 | 330 | kHz | Note 5 | 6 |
| EN Internal Pull High Current | | | 10 | 40 | A | VEN = 0V | 6 |
| EN Logic-High Input Voltage | VENH | 2 | | | V | | 6 |
| EN Logic-Low Input Voltage | VENL | | | 0.8 | V | | 6 |
| Over-Voltage Until PGOOD Goes Low | | | 880 | 902 | mV | Measured at FB, with respect to reference, no load | 6 |
| PGOOD Output Low Voltage | | | | 0.4 | V | ISINK = 1mA | 6 |
| PGOOD Leakage Current | ILEAK | | | 1 | A | High state, forced to 5V | 6 |
| UGATE Gate Driver Source | RUGATEsr | | 1.5 | 3 | Ω | VBOOT − VPHASE = 12V, ISOURCE = 100mA | 6 |
| UGATE Gate Driver Sink | RUGATEsk | | 2.25 | 4 | Ω | VBOOT − VPHASE = 12V, ISINK = 10mA | 6 |
| LGATE Gate Driver Source | RLGATEsr | | 1.5 | 3 | Ω | VCC = 12V, ISOURCE = 100mA | 6 |
| LGATE Gate Driver Sink | RLGATEsk | | 1 | 2 | Ω | VCC = 12V, ISOURCE = 10mA | 6 |
| Dead Time (UG falling to LG rising) | | 5 | 20 | | ns | From UG falling to LG rising, PHASE = 1.5V | 6 |
| Dead Time (LG falling to UG rising) | | 5 | 20 | | ns | From LG falling to UG rising | 6 |
| Internal Boot Charging Switch on Resistance | | | | 80 | Ω | VCC to BOOT, 10mA | 6 |
| Current Limit Setting Current | IOCSET | 9.5 | 10 | 10.5 | µA | | 7 |
| Current Limit Threshold Offset | | -20 | | 20 | mV | | 7 |
| Over Voltage Protection Threshold | VOVP | 0.95 | 1 | 1.03 | V | | 7 |
| Under Voltage Protection Threshold | VUVP | 0.57 | 0.6 | 0.63 | V | | 7 |
| Voltage Ramp Soft-Start Time | | 1.2 | 2 | 2.8 | ms | From FB 0% to FB 100% | 7 |
| Thermal Shutdown Threshold | TSD | 145 | | 165 | °C | | 7 |
| Reference Voltage | VREF | | 0.8 | | V | | 6 |
| Minimum On-Time | TON(MIN) | | 70 | | ns | | 6 |
| Minimum Off-Time | TOFF(MIN) | | 300 | | ns | | 6 |
| Under-Voltage Until PGOOD Goes Low | | | 720 | | mV | Measured at FB, with respect to reference, no load | 6 |
| Fault Propagation Delay | | | 1 | | µs | Falling edge, FB forced below PGOOD trip threshold | 6 |
| OVP latch delay | | | 5 | | µs | | 7 |
| Power Input Voltage | VIN | 2.5 | | 25 | V | | 5 |
| Control Voltage | VCC | 4.5 | | 13.2 | V | | 5 |
| Ambient Temperature Range | TA | -40 | | 85 | °C | | 5 |
| Junction Temperature Range | TJ | -40 | | 125 | °C | | 5 |
| VCC to GND | VCC | -0.3 | | 15 | V | | 5 |
| Other Pins | | -0.3 | | 6.5 | V | | 5 |
| BOOT to PHASE DC | | -0.3 | | 15 | V | DC | 5 |
| BOOT to PHASE | | -0.3 | | 20 | V | <100ns | 5 |
| PHASE to GND DC | | -5 | | 25 | V | DC | 5 |
| PHASE to GND | | -10 | | 30 | V | <100ns | 5 |
| BOOT to GND DC | | -0.3 | | 40 | V | DC | 5 |
| BOOT to GND | | -0.3 | | 45 | V | <100ns | 5 |
| UGATE to GND DC | | -0.3 | | 40 | V | DC | 5 |
| UGATE to GND | | -10 | | 45 | V | <100ns | 5 |
| UGATE to PHASE DC | | -0.3 | | 15 | V | DC | 5 |
| UGATE to PHASE | | -5 | | 20 | V | <40ns | 5 |
| LGATE to GND DC | | -0.3 | | 15 | V | DC | 5 |
| LGATE to GND | | -5 | | 20 | V | <100ns | 5 |
| Power Dissipation | PD | | | 3.27 | W | TA = 25C, WDFN-10L 3x3 | 5 |
| Lead Temperature | | | | 260 | °C | Soldering, 10 sec. | 5 |
| Junction Temperature | TJ | | | 150 | °C | | 5 |
| Storage Temperature Range | | -65 | | 150 | °C | | 5 |
| ESD Susceptibility HBM | | | | 2 | kV | HBM (Human Body Model) | 5 |
| Thermal Resistance Junction to Ambient | θJA | | 30.5 | | °C/W | WDFN-10L 3x3, JEDEC 51-7 four-layer board | 5 |
| Thermal Resistance Junction to Case | θJC | | 7.5 | | °C/W | WDFN-10L 3x3, at exposed pad | 5 |
## CAD (KiCad official)
- Symbol: `RT8129AGQW`
- Footprint: `Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm`
- 3D model: TDFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files: `rt8129agqw-etched.step` / `rt8129agqw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt8129agqw.step` / `rt8129agqw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Richtek Tech datasheet](docs/rt8129agqw-datasheet.pdf) (18 pp, sha256 `18c827b01f6fdd16`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/rt8129agqw-datasheet.pdf)