# RT8120AZSP

**Richtek Tech** · AC-DC Controllers & Regulators · SOP-8-EP

RT8120AZSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_in | Bootstrap power pin that powers the upper gate driver, with a bootstrap capacitor connected between BOOT and PHASE. |
| 2 | UGATE | output | Upper-gate driver output that connects to the gate of the high-side N-MOSFET and is monitored by adaptive shoot-through protection. |
| 3 | GND | power_in | Ground for the IC to which all voltage levels are referenced, connected to the low-side MOSFET source with the lowest impedance. |
| 4 | LGATE/OCSET | output | Lower-gate driver output powered from VCC that drives the low-side N-MOSFET gate, and during start-up sets the over-current threshold through a resistor ROCSET to GND. |
| 5 | VCC | power_in | Supply input for the controller and lower gate driver, to be connected to a well-decoupled 5V or 12V bias supply with VCC specified from 4.5V to 13.2V. |
| 6 | FB | input | Feedback input that is the inverting input of the error amplifier and senses the switch output through an external resistor divider. |
| 7 | COMP/EN | bidirectional | Feedback compensation pin that also serves as the enable input, where the chip is disabled when COMP is below 0.4V. |
| 8 | PHASE | passive | Switch node connected to the source of the upper MOSFET and the drain of the lower MOSFET. |
| 9 | GND | power_in | Exposed thermal pad that must be soldered to a large PCB and connected to GND for maximum power dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management ICs |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power On Reset Threshold | VCCR_TH | 3.9 | 4.1 | 4.3 | V | VCC Rising | 6 |
| Power On Reset Hysteresis | VCC_Hys | 0.26 | 0.45 | 0.64 | V |  | 6 |
| Switching Frequency | fOSC | 270 | 300 | 330 | kHz |  | 6 |
| Minimum Duty Cycle |  | 0 |  |  | % |  | 6 |
| Reference Voltage | VREF | 0.591 | 0.6 | 0.609 | V | RT8120A/C | 6 |
| Transconductance | gm | 500 | 700 |  | μA/V |  | 6 |
| Output Source Current | ICOMPSK | 80 | 120 |  | μA | VFB < VREF | 6 |
| Output Sink Current | ICOMPSC | 80 | 120 |  | μA | VFB < VREF | 6 |
| Under Voltage Protection | VUVP_FB | 65 | 75 | 80 | % |  | 6 |
| LGATE OC Setting Current | IOCSET | 9 | 10 | 11 | μA |  | 6 |
| Enable Threshold | VEN | 0.3 | 0.4 | 0.55 | V |  | 6 |
| Supply Input Voltage | VIN | 3 |  | 13.2 | V |  | 5 |
| Control Input Voltage | VCC | 4.5 |  | 13.2 | V |  | 5 |
| Junction Temperature Range |  | -40 |  | 125 | °C |  | 5 |
| Ambient Temperature Range |  | -40 |  | 85 | °C |  | 5 |
| VCC to GND | VCC |  |  | 15 | V |  | 5 |
| BOOT to PHASE | VBOOT-PHASE |  |  | 15 | V |  | 5 |
| PHASE to GND |  | -0.5 |  | 15 | V | DC | 5 |
| PHASE to GND |  | -8 |  | 25 | V | < 20ns | 5 |
| UGATE to PHASE |  | -0.3 |  |  | V | DC; max printed as (VBOOT-PHASE + 0.3V) | 5 |
| UGATE to PHASE |  | -5 |  |  | V | < 20ns; max printed as (VBOOT-PHASE + 5V) | 5 |
| LGATE to GND |  | -0.3 |  |  | V | DC; max printed as (VCC + 0.3V) | 5 |
| LGATE to GND |  | -5 |  |  | V | < 20ns; max printed as (VCC + 5V) | 5 |
| Other Pins |  | -0.3 |  | 7 | V |  | 5 |
| Power Dissipation SOP-8 (Exposed Pad) | PD |  |  | 3.26 | W | TA = 25°C | 5 |
| Lead Temperature |  |  |  | 260 | °C | Soldering, 10 sec. | 5 |
| Junction Temperature |  |  |  | 150 | °C |  | 5 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 5 |
| ESD Susceptibility HBM |  |  |  | 2 | kV | Human Body Model (Note 3) | 5 |
| Package Thermal Resistance SOP-8 (Exposed Pad) junction to ambient | θJA |  | 30.6 |  | °C/W |  | 5 |
| Package Thermal Resistance SOP-8 (Exposed Pad) junction to case | θJC |  | 3.4 |  | °C/W |  | 5 |

## CAD (KiCad official)

- Symbol: `RT8120AZSP`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `rt8120azsp-etched.step` / `rt8120azsp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt8120azsp.step` / `rt8120azsp.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Richtek Tech datasheet](docs/rt8120azsp-datasheet.pdf) (17 pp, sha256 `e5b94c43798d2143`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/rt8120azsp-datasheet.pdf)