Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	3d ago
viewers	rt7300bgs: viewers · Ray	3d ago
package.json	Publish 0.1.0 · Ray	3d ago
page.json	Set visibility: public · Ray	3d ago
README.md	Publish 0.1.0 · Ray	3d ago
rt7300bgs-etched.glb	Publish 0.1.0 · Ray	3d ago
rt7300bgs-etched.step	rt7300bgs: factory component page (tier=mfr) · Ray	3d ago
rt7300bgs-hero.glb	rt7300bgs: hero GLB from the etched model (keeps the MPN mark) · Ray	3d ago
rt7300bgs-hero.overlay.json	Publish 0.1.0 · Ray	3d ago
rt7300bgs.glb	Publish 0.1.0 · Ray	3d ago
rt7300bgs.kicad_mod	Publish 0.1.0 · Ray	3d ago
rt7300bgs.kicad_sym	Publish 0.1.0 · Ray	3d ago
rt7300bgs.lbr	Publish 0.1.0 · Ray	3d ago
rt7300bgs.step	Publish 0.1.0 · Ray	3d ago

RT7300BGS

Richtek Tech · AC-DC Controllers & Regulators · SOP-8

RT7300BGS from Richtek Tech, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	INV	input	Inverting input of the internal error amplifier (1.5V reference) connected to the output voltage divider, also used for OVP (1.65V threshold) and UVP detection.
2	COMP	output	Output of the internal error amplifier, where a compensation network to GND sets dynamic load performance; maximum COMP voltage is 4.25V min.
3	FF	input	Feed-forward input for line voltage sensed via a resistive divider, with a capacitor to filter line ripple and noise.
4	CS	input	Current sense input where the sense resistor to GND sets the current limit, with a 0.4V typical threshold.
5	ZCD	input	Zero current detection input from the PFC choke secondary winding for demagnetization timing, which also enables or disables the controller (disabled below 250mV).
6	GND	power_in	Ground of the controller.
7	GD	output	Gate driver output for the external power MOSFET, with 600mA source and 800mA sink capability and a 13V typical clamp.
8	VDD	power_in	Supply voltage input of 12V to 25V recommended, enabled above 16V typ. and disabled below 9V typ.

Key specifications

Parameter	Value
Manufacturer	Richtek Tech
Package	SOP-8
Category	Power Supply Chip
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VDD OVP Threshold Voltage	VOVP	25.5	27	28.5	V	VDD = 15V, TA = 25C	7
VDD On Threshold Voltage	VON_TH	15	16	17	V	VDD = 15V, TA = 25C	7
VDD Off Threshold Voltage	VOFF_TH	8	9	10	V	VDD = 15V, TA = 25C	7
Zener Voltage	VZ	29			V		7
Operating Supply Current	IDD_OP			2.5	mA	IZCD = 0, and GD open	7
Quiescent Current	IQ			1.7	mA	At burst mode, and GD open	7
Standby Current				0.6	mA	PFC is disabled	7
Start-Up Current	IDD_ST			20	µA	Before VON_TH	7
ZCD Upper Clamp Voltage	VZC_DH	4.5	4.8	5.5	V	IZCD = 2.5mA	7
ZCD Lower Clamp Voltage	VZC_DL	0.3	0.65		V	IZCD = 2.5mA	7
Delay Time Between Trigger Point and Gate Turn On			100	170	ns		7
ZCD Sourcing Current Capability		2.5		6.5	mA		7
ZCD Sinking Current Capability		2.5			mA		8
ZCD Disable Voltage	VZCD_DIS			250	mV		8
ZCD Restart Voltage	VZCD_EN	1			V		8
ZCD Pull-High Current After Disable		30	75	100	µA		8
FF Input Bias Current	IBIAS			1	µA	Leakage Current of FF Pin	8
Non-Inverting Input Reference	VREF	1.47	1.5	1.53	V		8
INV Bias Current				1	µA		8
Transconduction	gm	80	100	120	µA/V	/VERROR/ < 0.25V	8
COMP Maximum Voltage	VCOMP_OP	4.25			V		8
INV OVP Threshold Voltage		1.55	1.65	1.75	V		8
Burst Mode Entry Level High	VBURST_H	1.85	2.15	2.45	V	Measure at COMP Pin	8
Burst Mode Entry Level Low	VBURST_L	1.75	2.05	2.35	V	Measure at COMP Pin	8
De-bounce Time of Burst Mode		1.5	2	4	µs		8
Minimum On-Time	tON(MIN)_PFC	4.4	5.4	6.4	µs	= 3pF x 2.5V / (IZCD x 0.02), IZCD = 75µA	8
Leading Edge Blanking Time	tLEB_PFC	240	400	570	ns	LEB + Delay (Note 6)	8
Current Sense Threshold Voltage	VCS_PFC	0.35	0.4	0.45	V		8
Gate Driver Rising Time	tR		40	80	ns	CL = 1nF	8
Gate Driver Falling Time	tF		30	70	ns	CL = 1nF	8
Valley Mask Time	tMASK	7	8.5	10	µs		8
Duration of Starter	tSTART	75	130	300	µs		8
Supply Voltage	VDD	-0.3		30	V		7
Gate Driver Output	GD	-0.3		20	V		7
Other Pins		-0.3		6	V		7
Power Dissipation	PD			0.625	W	SOP-8, TA = 25°C	7
Junction Temperature	TJ			150	°C		7
Lead Temperature				260	°C	Soldering, 10 sec.	7
Storage Temperature Range		-65		150	°C		7
ESD Susceptibility HBM				2	kV	Human Body Model	7
ESD Susceptibility MM				200	V	Machine Model	7
Supply Voltage	VDD	12		25	V		7
Junction Temperature Range	TJ	-40		125	°C		7
Package Thermal Resistance, Junction to Ambient	θJA		160		°C/W	SOP-8, JEDEC 51-3 single-layer test board, TA = 25°C	7
VDD OVP De-bounce Time			10		µs		7
ZCD Arming Voltage	VZC_DA		1.6		V	Note 5	7
ZCD Trigger Voltage	VZC_DT		1		V	Note 5	7
Non-linear Gm			1		mA	/VERROR/ ≥ 0.25V	8
INV OVP De-bounce Time			20		µs		8
Ramp Slope			70		mV/µs	VFF=0.8V	8
Gate Output Clamping Voltage	VCLAMP		13		V	VDD = 25V	8
Internal Pull Low Resistor			12		kΩ		8
Maximum On-Time	tON(MAX)_PFC		50		µs		8

CAD (KiCad official)

Symbol: RT7300BGS
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOP-8 (KiCad packages3D, STEP)
3D model files: rt7300bgs-etched.step / rt7300bgs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rt7300bgs.step / rt7300bgs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Richtek Tech datasheet (14 pp, sha256 7a20e186868d2510, retrieved 2026-10-22, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF