# RT7272AGSP

**Richtek Tech** · DC-DC Converters · SOP-8-EP

RT7272AGSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switch node that connects to the external L-C filter (absolute maximum −0.3V to 40.3V). |
| 2 | BOOT | passive | Bootstrap supply for the high-side gate drive; a 100nF or greater capacitor is recommended from BOOT to SW (VBOOT−VSW max 6V). |
| 3 | EN | input | Enable control input; logic-high enables the converter and logic-low forces the device into shutdown mode. |
| 4 | GND | power_in | Ground; connected internally to exposed pad 9 and must be tied to GND. |
| 5 | FB | input | Feedback input connected to the converter output through a resistive divider to set the output voltage, regulating to 0.8V reference. |
| 6 | COMP | passive | Compensation node for the regulation control loop; connect a series RC network from COMP to GND, with an additional capacitor to GND in some cases. |
| 7 | RLIM | passive | Current limit setting; connect a resistor to determine the current limit (1.9A to 7A range). |
| 8 | VIN | power_in | Power input with a 4.5V to 36V input voltage range; must be bypassed with a suitable large ceramic capacitor. |
| 9 | GND | power_in | Exposed pad ground; must be soldered to a large PCB area and connected to GND for maximum thermal dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Supply Chip |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Reference Voltage | VREF | 0.788 | 0.8 | 0.812 | V | 4.5V ≤ VIN ≤ 36V | 4 |
| Shutdown Supply Current |  |  | 0.5 | 3 | µA | VEN = 0V | 4 |
| Quiescent Current | IQ |  | 0.9 | 1.2 | mA | VEN = 3V, VFB = 0.9V | 4 |
| High Side Switch Leakage Current |  |  | 0 | 10 | µA | VEN = 0V, VSW = 0V | 4 |
| Upper Switch Current Limit Range | UOC | 1.9 |  | 7 | A |  | 4 |
| Upper Switch Current Limit | UOC | 1.9 | 2.5 | 3.1 | A | Min. duty cycle, RLIM = 57.6kΩ | 4 |
| Upper Switch Current Limit | UOC | 2.7 | 3.5 | 4.2 | A | Min. duty cycle, RLIM = 84.5kΩ | 4 |
| Upper Switch Current Limit | UOC | 4.8 | 5.5 | 6.3 | A | Min. duty cycle, RLIM = 137kΩ | 4 |
| Oscillation Frequency | fOSC1 | 450 | 500 | 550 | kHz |  | 5 |
| EN Input Voltage Logic-High | VIH | 1.4 | 1.65 | 2 | V |  | 5 |
| EN Input Voltage Logic-Low | VIL | 1.2 | 1.45 | 1.9 | V |  | 5 |
| Input Under Voltage Lockout Threshold | VUVLO | 3.9 | 4.1 | 4.3 | V | VIN rising | 5 |
| Load Regulation | ∆VLOAD |  |  | 0.05 | %/A |  | 5 |
| Line Regulation | ∆VLINE |  |  | 0.1 | % | VIN = 4.5V to 36V | 5 |
| High Side Switch On-Resistance | RDS(ON)1 |  | 150 |  | mΩ |  | 4 |
| Low Side Switch On-Resistance | RDS(ON)2 |  | 80 |  | mΩ |  | 4 |
| Lower Switch Current Limit |  |  | 1.5 |  | A | From drain to source | 4 |
| Short Circuit Oscillation Frequency | fOSC2 |  | 75 |  | kHz | VFB = 0V | 5 |
| Maximum Duty Cycle | DMAX |  | 90 |  | % | VFB = 0.7V | 5 |
| Minimum On-Time | tON_MIN |  | 100 |  | ns |  | 5 |
| EN Logic-High Hysteresis | ∆VIH |  | 0.2 |  | V |  | 5 |
| UVLO Hysteresis | ∆VUVLO |  | 250 |  | mV |  | 5 |
| Thermal Shutdown | TSD |  | 150 |  | °C |  | 5 |
| Thermal Shutdown Hysteresis | ∆TSD |  | 20 |  | °C |  | 5 |
| COMP to Current Sense Transconductance | GCS |  | 4.7 |  | A/V | ∆ICOMP = ±10µA | 5 |
| Error Amplifier Transconductance | GEA |  | 1000 |  | µA/V |  | 5 |
| Supply Input Voltage | VIN | 4.5 |  | 36 | V |  | 4 |
| Junction Temperature Range | TJ | -40 |  | 125 | °C |  | 4 |
| Ambient Temperature Range | TA | -40 |  | 85 | °C |  | 4 |
| Supply Input Voltage | VIN | -0.3 |  | 40 | V |  | 4 |
| Switch Voltage | SW | -0.3 |  | 40.3 | V |  | 4 |
| Switch Voltage | SW | -5 |  | 46 | V | t < 10ns | 4 |
| BOOT to SW Voltage | VBOOT − VSW | -0.3 |  | 6 | V |  | 4 |
| Other Pins Voltage |  | -0.3 |  | 40 | V |  | 4 |
| Power Dissipation | PD |  |  | 2.041 | W | TA = 25°C, SOP-8 (Exposed Pad) | 4 |
| Lead Temperature |  |  |  | 260 | °C | Soldering, 10 sec. | 4 |
| Junction Temperature | TJ |  |  | 150 | °C |  | 4 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 4 |
| ESD Susceptibility HBM |  |  |  | 2 | kV | HBM (Human Body Model) | 4 |
| Thermal Resistance Junction to Ambient | θJA |  |  | 49 | °C/W | SOP-8 (Exposed Pad), JEDEC 51-7 four-layer board | 4 |
| Thermal Resistance Junction to Case | θJC |  |  | 15 | °C/W | SOP-8 (Exposed Pad), measured at exposed pad | 4 |

## CAD (KiCad official)

- Symbol: `RT7272AGSP`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `rt7272agsp-etched.step` / `rt7272agsp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt7272agsp.step` / `rt7272agsp.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Richtek Tech datasheet](docs/rt7272agsp-datasheet.pdf) (14 pp, sha256 `4fe86b9aa2c60994`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/rt7272agsp-datasheet.pdf)