component
RT7270HZSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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RT7270HZSP
Richtek Tech · DC-DC Converters · SOP-8-EP
RT7270HZSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap for high side gate driver; connect a 0.1μF or greater ceramic capacitor from BOOT to SW. |
| 2 | VIN | power_in | Input supply voltage, 4.5V to 18V; must be bypassed with a suitable large ceramic capacitor. |
| 3 | SW | power_out | Switch node; connect to an external L-C filter. |
| 4 | GND | power_in | Ground; the exposed pad (pin 9) must be soldered to a large PCB and connected to GND for maximum power dissipation. |
| 5 | FB | input | Feedback input used to regulate the output to a set value via an external resistive voltage divider (0.925V reference typ.). |
| 6 | COMP | passive | Compensation node for the regulation control loop; connect a series RC network from COMP to GND, sometimes with an additional capacitor. |
| 7 | EN | input | Enable input; logic high enables the converter, logic low (<0.4V) forces shutdown with supply current below 3μA. |
| 8 | SS | passive | Soft-start control input; a capacitor from SS to GND sets the soft-start period (0.1μF gives 15.5ms). |
| 9 | GND | power_in | Exposed pad, ground; must be soldered to a large PCB and connected to GND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management ICs |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown Supply Current | 0.5 | 3 | μA | VEN = 0V | 4 | ||
| Supply Current | 0.8 | 1.2 | mA | VEN = 3V, VFB = 0.9V | 4 | ||
| Reference Voltage | VREF | 0.911 | 0.925 | 0.939 | V | 4.5V ≤ VIN ≤ 18V | 4 |
| High Side Switch Leakage Current | 0 | 10 | μA | VEN = 0V, VSW = 0V | 4 | ||
| Oscillation Frequency | fOSC1 | 300 | 340 | 380 | kHz | 4 | |
| EN Input Threshold Logic-High | VIH | 2.7 | 18 | V | 5 | ||
| EN Input Threshold Logic-Low | VIL | 0.4 | V | 5 | |||
| Input Under Voltage Lockout Threshold | VUVLO | 3.8 | 4.2 | 4.5 | V | VIN Rising | 5 |
| Supply Input Voltage | VIN | -0.3 | 20 | V | 4 | ||
| Switch Voltage | SW | -0.3 | V | upper limit VIN + 0.3V | 4 | ||
| VBOOT − VSW | -0.3 | 6 | V | 4 | |||
| Other Pins Voltage | -0.3 | 20 | V | 4 | |||
| Power Dissipation | PD | 1.333 | W | TA = 25°C, SOP-8 (Exposed Pad) | 4 | ||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 4 | |||
| Junction Temperature | TJ | 150 | °C | 4 | |||
| Storage Temperature Range | -65 | 150 | °C | 4 | |||
| ESD HBM | 2 | kV | Human Body Mode | 4 | |||
| ESD MM | 200 | V | Machine Mode | 4 | |||
| Supply Input Voltage | VIN | 4.5 | 18 | V | 4 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 4 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 4 | ||
| Thermal Resistance Junction to Ambient | θJA | 75 | °C/W | SOP-8 (Exposed Pad) | 4 | ||
| Thermal Resistance Junction to Case | θJC | 15 | °C/W | SOP-8 (Exposed Pad) | 4 | ||
| Error Amplifier Transconductance | GEA | 940 | μA/V | ΔIC = ±10μA | 4 | ||
| High Side Switch On-Resistance | RDS(ON)1 | 110 | mΩ | 4 | |||
| Low Side Switch On-Resistance | RDS(ON)2 | 90 | mΩ | 4 | |||
| Upper Switch Current Limit | 5.1 | A | Min. Duty Cycle, VBOOT − VSW = 4.8V | 4 | |||
| COMP to Current Sense Transconductance | GCS | 5.1 | A/V | 4 | |||
| Short Circuit Oscillation Frequency | fOSC2 | 100 | kHz | VFB = 0V | 4 | ||
| Maximum Duty Cycle | DMAX | 93 | % | VFB = 0.7V | 5 | ||
| Minimum On Time | tON | 100 | ns | 5 | |||
| Input Under Voltage Lockout Hysteresis | ΔVUVLO | 320 | mV | 5 | |||
| Soft-Start Current | ISS | 6 | μA | VSS = 0V | 5 | ||
| Soft-Start Period | tSS | 15.5 | ms | CSS = 0.1μF | 5 | ||
| Thermal Shutdown | TSD | 150 | °C | 5 |
CAD (KiCad official)
- Symbol:
RT7270HZSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (14 pp, sha256
7a053d354c72b905, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# RT7270HZSP
**Richtek Tech** · DC-DC Converters · SOP-8-EP
RT7270HZSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap for high side gate driver; connect a 0.1μF or greater ceramic capacitor from BOOT to SW. |
| 2 | VIN | power_in | Input supply voltage, 4.5V to 18V; must be bypassed with a suitable large ceramic capacitor. |
| 3 | SW | power_out | Switch node; connect to an external L-C filter. |
| 4 | GND | power_in | Ground; the exposed pad (pin 9) must be soldered to a large PCB and connected to GND for maximum power dissipation. |
| 5 | FB | input | Feedback input used to regulate the output to a set value via an external resistive voltage divider (0.925V reference typ.). |
| 6 | COMP | passive | Compensation node for the regulation control loop; connect a series RC network from COMP to GND, sometimes with an additional capacitor. |
| 7 | EN | input | Enable input; logic high enables the converter, logic low (<0.4V) forces shutdown with supply current below 3μA. |
| 8 | SS | passive | Soft-start control input; a capacitor from SS to GND sets the soft-start period (0.1μF gives 15.5ms). |
| 9 | GND | power_in | Exposed pad, ground; must be soldered to a large PCB and connected to GND for maximum power dissipation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management ICs |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown Supply Current | | | 0.5 | 3 | μA | VEN = 0V | 4 |
| Supply Current | | | 0.8 | 1.2 | mA | VEN = 3V, VFB = 0.9V | 4 |
| Reference Voltage | VREF | 0.911 | 0.925 | 0.939 | V | 4.5V ≤ VIN ≤ 18V | 4 |
| High Side Switch Leakage Current | | | 0 | 10 | μA | VEN = 0V, VSW = 0V | 4 |
| Oscillation Frequency | fOSC1 | 300 | 340 | 380 | kHz | | 4 |
| EN Input Threshold Logic-High | VIH | 2.7 | | 18 | V | | 5 |
| EN Input Threshold Logic-Low | VIL | | | 0.4 | V | | 5 |
| Input Under Voltage Lockout Threshold | VUVLO | 3.8 | 4.2 | 4.5 | V | VIN Rising | 5 |
| Supply Input Voltage | VIN | -0.3 | | 20 | V | | 4 |
| Switch Voltage | SW | -0.3 | | | V | upper limit VIN + 0.3V | 4 |
| VBOOT − VSW | | -0.3 | | 6 | V | | 4 |
| Other Pins Voltage | | -0.3 | | 20 | V | | 4 |
| Power Dissipation | PD | | | 1.333 | W | TA = 25°C, SOP-8 (Exposed Pad) | 4 |
| Lead Temperature | | | | 260 | °C | Soldering, 10 sec. | 4 |
| Junction Temperature | TJ | | | 150 | °C | | 4 |
| Storage Temperature Range | | -65 | | 150 | °C | | 4 |
| ESD HBM | | | | 2 | kV | Human Body Mode | 4 |
| ESD MM | | | | 200 | V | Machine Mode | 4 |
| Supply Input Voltage | VIN | 4.5 | | 18 | V | | 4 |
| Junction Temperature Range | TJ | -40 | | 125 | °C | | 4 |
| Ambient Temperature Range | TA | -40 | | 85 | °C | | 4 |
| Thermal Resistance Junction to Ambient | θJA | | | 75 | °C/W | SOP-8 (Exposed Pad) | 4 |
| Thermal Resistance Junction to Case | θJC | | | 15 | °C/W | SOP-8 (Exposed Pad) | 4 |
| Error Amplifier Transconductance | GEA | | 940 | | μA/V | ΔIC = ±10μA | 4 |
| High Side Switch On-Resistance | RDS(ON)1 | | 110 | | mΩ | | 4 |
| Low Side Switch On-Resistance | RDS(ON)2 | | 90 | | mΩ | | 4 |
| Upper Switch Current Limit | | | 5.1 | | A | Min. Duty Cycle, VBOOT − VSW = 4.8V | 4 |
| COMP to Current Sense Transconductance | GCS | | 5.1 | | A/V | | 4 |
| Short Circuit Oscillation Frequency | fOSC2 | | 100 | | kHz | VFB = 0V | 4 |
| Maximum Duty Cycle | DMAX | | 93 | | % | VFB = 0.7V | 5 |
| Minimum On Time | tON | | 100 | | ns | | 5 |
| Input Under Voltage Lockout Hysteresis | ΔVUVLO | | 320 | | mV | | 5 |
| Soft-Start Current | ISS | | 6 | | μA | VSS = 0V | 5 |
| Soft-Start Period | tSS | | 15.5 | | ms | CSS = 0.1μF | 5 |
| Thermal Shutdown | TSD | | 150 | | °C | | 5 |
## CAD (KiCad official)
- Symbol: `RT7270HZSP`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOP-8-EP (KiCad packages3D, STEP)
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Richtek Tech datasheet](docs/rt7270hzsp-datasheet.pdf) (14 pp, sha256 `7a053d354c72b905`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/rt7270hzsp-datasheet.pdf)