component
RT7257BHZSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOIC-8-EP. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.md+14@@ -37,6 +37,20 @@ RT7257BHZSP from Richtek Tech, in a SOIC-8-EP. Pinout and pin descriptions extra - Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm` - 3D model: SOIC-8-EP (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`rt7257bhzsp.step`](rt7257bhzsp.step) | 125 KB | You want the bare part, or you mark your own boards. |+| [`rt7257bhzsp-etched.step`](rt7257bhzsp-etched.step) | 2.1 MB | You want the part with `RT7257BHZSP` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 531 faces against 152 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1@@ -1,6 +1,6 @@ { "slug": "rt7257bhzsp",- "version": "0.1.0",+ "version": "0.2.0", "type": "component", "description": "Richtek Tech DC-DC Converters, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "tags": [
page.json+14−11@@ -4,7 +4,7 @@ "slug": "rt7257bhzsp", "title": "RT7257BHZSP", "brief": "Richtek Tech DC-DC Converters, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.2.0", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -34,31 +34,31 @@ "number": "1", "name": "BOOT", "type": "power_in",- "description": "Bootstrap for high-side gate driver. Connect a 0.1\u03bcF or greater ceramic capacitor from BOOT to SW. V(BOOT)-V(SW) absolute max 6V."+ "description": "Bootstrap for high-side gate driver. Connect a 0.1μF or greater ceramic capacitor from BOOT to SW. V(BOOT)-V(SW) absolute max 6V." }, { "number": "2", "name": "VIN", "type": "power_in",- "description": "Input supply voltage, 4.5V to 18V (abs max 20V). Must be bypassed with a suitable large ceramic capacitor (e.g. 10\u03bcF x2 + 0.1\u03bcF)."+ "description": "Input supply voltage, 4.5V to 18V (abs max 20V). Must be bypassed with a suitable large ceramic capacitor (e.g. 10μF x2 + 0.1μF)." }, { "number": "3", "name": "SW", "type": "power_out",- "description": "Switch node. Connect to an external L-C output filter. Swings between GND and VIN at up to 1.2MHz. High-side RDS(on) 110m\u03a9, low-side 90m\u03a9."+ "description": "Switch node. Connect to an external L-C output filter. Swings between GND and VIN at up to 1.2MHz. High-side RDS(on) 110mΩ, low-side 90mΩ." }, { "number": "4", "name": "GND", "type": "power_in",- "description": "Ground. Pin 4 and the exposed pad (pin 9) must both be soldered to a large PCB copper area connected to GND for maximum power dissipation (\u03b8JA 75\u00b0C/W with exposed pad)."+ "description": "Ground. Pin 4 and the exposed pad (pin 9) must both be soldered to a large PCB copper area connected to GND for maximum power dissipation (θJA 75°C/W with exposed pad)." }, { "number": "5", "name": "FB", "type": "input",- "description": "Feedback input. Regulates the output via an external resistive voltage divider. Internal reference VREF = 0.8V (\u00b11.5%)."+ "description": "Feedback input. Regulates the output via an external resistive voltage divider. Internal reference VREF = 0.8V (±1.5%)." }, { "number": "6",@@ -70,19 +70,19 @@ "number": "7", "name": "EN", "type": "input",- "description": "Enable input. Logic high (VIH \u2265 2.7V) enables the converter; logic low (VIL \u2264 0.4V) puts the device into shutdown (<3\u03bcA supply). Tie to VIN via a 100k\u03a9 pull-up for automatic startup. Absolute max 20V."+ "description": "Enable input. Logic high (VIH ≥ 2.7V) enables the converter; logic low (VIL ≤ 0.4V) puts the device into shutdown (<3μA supply). Tie to VIN via a 100kΩ pull-up for automatic startup. Absolute max 20V." }, { "number": "8", "name": "SS", "type": "input",- "description": "Soft-start control input. Connect a capacitor from SS to GND to set the soft-start period; a 0.1\u03bcF cap gives ~13.5ms (ISS = 6\u03bcA typ)."+ "description": "Soft-start control input. Connect a capacitor from SS to GND to set the soft-start period; a 0.1μF cap gives ~13.5ms (ISS = 6μA typ)." }, { "number": "9", "name": "GND", "type": "power_in",- "description": "Ground. Pin 4 and the exposed pad (pin 9) must both be soldered to a large PCB copper area connected to GND for maximum power dissipation (\u03b8JA 75\u00b0C/W with exposed pad)."+ "description": "Ground. Pin 4 and the exposed pad (pin 9) must both be soldered to a large PCB copper area connected to GND for maximum power dissipation (θJA 75°C/W with exposed pad)." } ], "provenance": {@@ -156,6 +156,9 @@ "docs/hero.png", "docs/rt7257bhzsp-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"- ]+ "viewers/footprint.html",+ "pads.json"+ ],+ "description": "Richtek Tech DC-DC Converters, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "visibility": "public" }