component
RT7233GSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownRT7233GSP
Richtek Tech · DC-DC Converters · SOP-8-EP
RT7233GSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable control input; logic-high (>1.25V, up to 18V) enables the converter and logic-low (<0.85V) forces shutdown, reducing supply current to less than 10µA. |
| 2 | FB | input | Feedback voltage input used to regulate the output to a set value via an external resistive divider; the feedback threshold voltage is 0.765V typically. |
| 3 | VREG5 | power_out | Internal regulator output; connect a 1µF capacitor to GND to stabilize the output voltage. |
| 4 | SS | passive | Soft-start time setting; connect an external capacitor between this pin and GND to set the soft-start time. |
| 5 | PGND | power_in | Power ground. |
| 6 | SW | power_out | Switch node; connect this pin to an external L-C filter. |
| 7 | BOOT | passive | Bootstrap supply for the high side gate driver; connect a 0.1µF capacitor between the BOOT and SW pins. |
| 8 | VIN | power_in | Power input with a 4.5V to 18V input voltage range; must be bypassed with a suitably large (10µF x 2) ceramic capacitor. |
| 9 | PGND | power_in | Power ground exposed pad; must be soldered to a large PCB area and connected to PGND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Supply Chip |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown Current | ISHDN | 1 | 10 | µA | VEN = 0V | 5 | |
| Quiescent Current | IQ | 1 | 1.3 | mA | VEN = 5V, VFB = 0.8V | 5 | |
| EN Input Voltage Logic-High | 1.25 | 18 | V | 5 | |||
| EN Input Voltage Logic-Low | 0.85 | V | 5 | ||||
| Feedback Threshold Voltage | VFB | 0.757 | 0.765 | 0.773 | V | TA = 25°C | 5 |
| Feedback Threshold Voltage | VFB | 0.755 | 0.775 | V | TA = -40°C to 85°C | 5 | |
| Feedback Input Current | IFB | 0.01 | 0.1 | µA | VFB = 0.8V | 5 | |
| VREG5 Output Voltage | VREG5 | 4.8 | 5.1 | 5.4 | V | 6V ≤ VIN ≤ 18V, 0 < IVREG5 ≤ 5mA | 6 |
| VREG5 Line Regulation | 20 | mV | 6V ≤ VIN ≤ 18V, IVREG5 = 5mA | 6 | |||
| VREG5 Load Regulation | 100 | mV | 0 ≤ IVREG5 ≤ 5mA | 6 | |||
| Current Limit | ILIM | 4.9 | 5.85 | 6.8 | A | 6 | |
| Minimum Off-Time | tOFF(MIN) | 260 | 310 | ns | VFB = 0.7V | 6 | |
| SS Charge Current | 5 | 6 | 8 | µA | VSS = 0V | 6 | |
| SS Discharge Current | 0.1 | 0.2 | mA | VSS = 0.5V | 6 | ||
| UVLO Threshold Wake Up | 3.6 | 3.85 | 4.1 | V | VREG5 | 6 | |
| UVLO Hysteresis | 0.16 | 0.35 | 0.47 | V | 6 | ||
| Supply Voltage | VIN | 4.5 | 18 | V | 5 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 5 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 5 | ||
| Supply Voltage VIN, VCC | VIN, VCC | -0.3 | 20 | V | 5 | ||
| Switch Voltage SW | SW | -0.8 | V | max = VIN + 0.3V | 5 | ||
| Switch Voltage SW | SW | -5 | 25 | V | < 10ns | 5 | |
| BOOT to SW | -0.3 | 6 | V | 5 | |||
| EN | EN | -0.3 | 20 | V | 5 | ||
| Other Pins | -0.3 | 6 | V | 5 | |||
| Power Dissipation SOP-8 (Exposed Pad) | PD | 2.174 | W | TA = 25°C | 5 | ||
| Junction Temperature | TJ | 150 | °C | 5 | |||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 5 | |||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| ESD HBM | 3 | kV | 5 | ||||
| ESD MM | 250 | V | 5 | ||||
| Thermal Resistance Junction-to-Ambient SOP-8 (EP) | θJA | 46 | °C/W | 5 | |||
| Thermal Resistance Junction-to-Case SOP-8 (EP) | θJC | 7 | °C/W | 5 | |||
| High-Side RDS(ON) | RDS(ON)_H | 120 | mΩ | (VBOOT − VSW) = 5.5V | 6 | ||
| Low-Side RDS(ON) | RDS(ON)_L | 50 | mΩ | 6 | |||
| VREG5 Output Current | IVREG5 | 70 | mA | VIN = 6V, VREG5 = 4V | 6 | ||
| Thermal Shutdown Threshold | TSD | 150 | °C | Shutdown Temperature | 6 | ||
| Thermal Shutdown Hysteresis | ΔTSD | 20 | °C | 6 | |||
| On-Time | tON | 135 | ns | VIN = 12V, VOUT = 1.05V | 6 |
CAD (KiCad official)
- Symbol:
RT7233GSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
rt7233gsp-etched.step/rt7233gsp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt7233gsp.step/rt7233gsp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (18 pp, sha256
e6988c3715c304d1, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).