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RT6576DGQW
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Richtek Tech DC-DC Converters, WQFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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| README.md | 14d ago |
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| rt6576dgqw-etched.step | 14d ago |
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| rt6576dgqw.glb | 14d ago |
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RT6576DGQW
Richtek Tech · DC-DC Converters · WQFN-20-EP(3x3)
RT6576DGQW from Richtek Tech, in a WQFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS1 | input | Channel 1 current-limit setting input: a resistor to GND sets the threshold to 1/8 of the CS1 voltage over a 0.2V to 2V range, fed by an internal 10µA source from LDO5. |
| 2 | FB1 | input | Channel 1 feedback input: a resistive divider from VOUT1 to GND sets the output from 2V to 5.5V. |
| 3 | LDO3 | power_out | 3.3V linear regulator output that is always on when VIN is above the VINPOR threshold, rated up to 100mA. |
| 4 | FB2 | input | Channel 2 feedback input: a resistive divider from VOUT2 to GND sets the output from 2V to 4V. |
| 5 | CS2 | input | Channel 2 current-limit setting input: a resistor to GND sets the threshold to 1/8 of the CS2 voltage over a 0.2V to 2V range, fed by an internal 10µA source from LDO5. |
| 6 | EN2 | input | Channel 2 enable input with 1.6V minimum logic-high and 0.4V maximum logic-low thresholds. |
| 7 | PGOOD | output | Open-drain power-good output for Channel 1 and Channel 2 (logical AND) that requires a pull-up resistor and is released when both outputs are above 88% of nominal. |
| 8 | PHASE2 | passive | Channel 2 switch node that serves as the internal lower supply rail for the UGATE2 driver and as the Channel 2 current-sense input. |
| 9 | BOOT2 | power_out | Bootstrap supply for the Channel 2 high-side gate driver, connected to an external capacitor per the typical application circuit. |
| 10 | UGATE2 | output | Channel 2 high-side gate driver output that swings between PHASE2 and BOOT2. |
| 11 | LGATE2 | output | Channel 2 low-side gate driver output that swings between GND and LDO5. |
| 12 | VIN | power_in | Power input for the 5V and 3.3V LDO regulators and buck controllers, with a 5V to 25V recommended operating range and 30V absolute maximum. |
| 13 | LDO5 | power_out | 5V linear regulator output that also supplies the low-side MOSFET gate drivers and the analog circuitry, rated up to 100mA. |
| 14 | BYP1 | power_in | Switch-over source input for LDO5 that connects to the Channel 1 output, bypassing LDO5 once VOUT1 exceeds the 4.66V threshold. |
| 15 | LGATE1 | output | Channel 1 low-side gate driver output that swings between GND and LDO5. |
| 16 | UGATE1 | output | Channel 1 high-side gate driver output that swings between PHASE1 and BOOT1. |
| 17 | BOOT1 | power_out | Bootstrap supply for the Channel 1 high-side gate driver, connected to an external capacitor per the typical application circuit. |
| 18 | PHASE1 | passive | Channel 1 switch node that serves as the internal lower supply rail for the UGATE1 driver and as the Channel 1 current-sense input. |
| 19 | VCLK | output | Oscillator output for an external charge pump, operating at a typical 260kHz and driven from BYP1. |
| 20 | EN1 | input | Channel 1 enable input with 1.6V minimum logic-high and 0.4V maximum logic-low thresholds. |
| 21 | GND | power_in | Ground exposed pad that must be soldered to a large PCB and connected to GND for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | WQFN-20-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Power-On Reset Rising Threshold | VINPOR | 4.6 | 4.9 | V | 7 | ||
| VIN Power-On Reset Falling Threshold | VINPOR | 3.2 | 3.7 | V | 7 | ||
| VIN Standby Supply Current (RT6576D) | IVIN_SBY | 80 | 100 | µA | Both Buck Controllers Off, VEN1 = VEN2 = GND | 7 | |
| VIN Quiescent Current | IVIN_nosw | 15 | 25 | µA | Both Buck Controllers On, VFBx = 2.05V, VBYP1 = 5.05V | 7 | |
| BYP1 Supply Current | IBYP1_nosw | 420 | 500 | µA | Both Buck Controllers On, VFBx = 2.05V, VBYP1 = 5.05V | 7 | |
| FBx Valley Trip Voltage | VFBx | 1.98 | 2 | 2.02 | V | CCM Operation | 7 |
| BYP1 Discharge Current | IDCHG_BYP1 | 10 | 45 | mA | VBYP1 = 0.5V | 7 | |
| PHASEx Discharge Current | IDCHG_LX | 5 | 8 | mA | VPHASEx = 0.5V | 7 | |
| Switching Frequency CH1 | fSWx | 240 | 300 | 360 | kHz | VIN = 20V, VOUT1 = 5V | 7 |
| Switching Frequency CH2 | fSWx | 280 | 355 | 430 | kHz | VIN = 20V, VOUT2 = 3.33V | 7 |
| Minimum Off-Time | tOFF(MIN) | 200 | 275 | ns | VFBx = 1.9V | 7 | |
| Soft-Start Time | tSSx | 2 | 4.5 | ms | VOUTx Ramp-up Time | 7 | |
| CSx Source Current | ICSx | 9 | 10 | 11 | µA | VCSx = 1V, VFBx = 1.9V | 7 |
| LDO5 Output Voltage | VLDO5 | 4.9 | 5 | 5.1 | V | VIN = 12V, No Load | 7 |
| LDO5 Output Voltage | VLDO5 | 4.8 | 5 | 5.1 | V | VIN > 7V, ILDO5 < 100mA | 7 |
| LDO5 Output Voltage | VLDO5 | 4.5 | 4.75 | 5.1 | V | VIN > 5V, ILDO5 < 20mA | 7 |
| LDO3 Output Voltage | VLDO3 | 3.267 | 3.3 | 3.333 | V | VIN = 12V, No Load | 7 |
| LDO3 Output Voltage | VLDO3 | 3.217 | 3.3 | 3.383 | V | VIN > 7V, ILDO3 < 100mA | 7 |
| LDO5 Output Current | ILDO5 | 100 | 175 | mA | VLDO5 = 4.5V, VBYP1 = GND, VIN = 7.4V | 8 | |
| LDO3 Output Current | ILDO3 | 100 | 175 | mA | VLDO3 = 3V, VIN = 7.4V | 8 | |
| LDO5 Switch-over Equivalent Resistance | RSW | 1.5 | 3 | Ω | LDO5 to BYP1, 10mA | 8 | |
| LDO5 UVLO Threshold Rising Edge | VUVLO5 | 4.3 | 4.6 | V | Rising Edge | 8 | |
| LDO5 UVLO Threshold Falling Edge | VUVLO5 | 3.7 | 3.9 | 4.1 | V | Falling Edge | 8 |
| PGOOD Threshold | VPGxTH | 84 | 88 | 92 | % | PGOOD Detect, VFBx Rising Edge | 8 |
| PGOOD Leakage Current | 1 | µA | High state, VPGOOD = 5.5V | 8 | |||
| PGOOD Output Low Voltage | 0.3 | V | ISINK = 4mA | 8 | |||
| OVP Trip Threshold | VOVP | 109 | 113 | 117 | % | FBx with Respect to Internal Reference | 8 |
| UVP Trip Threshold | VUVP | 47 | 52 | 57 | % | UVP Detect, FBx Falling Edge | 8 |
| ENx Threshold Voltage Logic-High | VENx_H | 1.6 | V | SMPS On | 8 | ||
| ENx Threshold Voltage Logic-Low | VENx_L | 0.4 | V | SMPS Off | 8 | ||
| VIN to GND | -0.3 | 30 | V | 6 | |||
| BOOTx to GND | -0.3 | 36 | V | DC | 6 | ||
| BOOTx to GND | -5 | 42 | V | <100ns | 6 | ||
| BOOTx to PHASEx | -0.3 | 6 | V | DC | 6 | ||
| BOOTx to PHASEx | -5 | 7.5 | V | <100ns | 6 | ||
| PHASEx to GND | -5 | 30 | V | DC | 6 | ||
| PHASEx to GND | -10 | 42 | V | <100ns | 6 | ||
| UGATEx to GND | -5 | 36 | V | DC | 6 | ||
| UGATEx to GND | -10 | 42 | V | <100ns | 6 | ||
| UGATEx to PHASEx | -0.3 | 6 | V | DC | 6 | ||
| UGATEx to PHASEx | -5 | 7.5 | V | <100ns | 6 | ||
| LGATEx to GND | -0.3 | 6 | V | DC | 6 | ||
| LGATEx to GND | -5 | 7.5 | V | <100ns | 6 | ||
| Other Pins | -0.3 | 6.5 | V | 6 | |||
| Power Dissipation | PD | 3.33 | W | TA = 25°C, WQFN-20L 3x3 | 6 | ||
| Junction Temperature | 150 | °C | 6 | ||||
| Lead Temperature | 260 | °C | Soldering, 10 sec. | 6 | |||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| ESD Susceptibility HBM | 2 | kV | HBM (Human Body Model) | 6 | |||
| Package Thermal Resistance Junction-to-Ambient | θJA | 30 | °C/W | WQFN-20L 3x3 | 6 | ||
| Package Thermal Resistance Junction-to-Case | θJC | 7.5 | °C/W | WQFN-20L 3x3 | 6 | ||
| Supply Voltage | VIN | 5 | 25 | V | 6 | ||
| Junction Temperature Range | -40 | 125 | °C | 6 | |||
| Ambient Temperature Range | -40 | 85 | °C | 6 |
CAD (KiCad official)
- Symbol:
RT6576DGQW - Footprint:
Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm - 3D model: WQFN-20-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
rt6576dgqw-etched.step/rt6576dgqw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt6576dgqw.step/rt6576dgqw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (22 pp, sha256
7f62ce8acae8f459, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).