component
RT6363GSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownRT6363GSP
Richtek Tech · DC-DC Converters · SOP-8-EP
RT6363GSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap capacitor connection node that supplies the high-side gate driver; connect a 0.1µF ceramic capacitor between this pin and SW. |
| 2 | VIN | power_in | Power input with an input voltage range of 4V to 60V; connect a suitable input capacitor to GND, usually two 2.2µF or larger ceramic capacitors with one typical value of 4.7µF. |
| 3 | EN | input | Enable control with an internal pull-up current source; float or drive to logic-high (≥1.2V) to enable the converter, and drive logic-low to force shutdown mode. |
| 4 | RT/SYNC | input | Frequency setting and external synchronization input; a resistor from this pin to GND sets the switching frequency, or a clock source can be tied here to synchronize to an external frequency. |
| 5 | FB | input | Output voltage sense input through a resistive divider, with a feedback reference voltage of 0.8V typically. |
| 6 | COMP | passive | Compensation node; external compensation elements connected to this pin stabilize the control loop. |
| 7 | GND | power_in | Ground pin that provides the ground return path for the control circuitry. |
| 8 | SW | output | Switch node that supplies power to the output; the output LC filter connects from SW to the output load. |
| 9 | PAD | passive | Exposed pad, internally unconnected, that must be soldered to a large PCB copper area for maximum power dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage, VIN | VIN | -0.3 | 65 | V | 10 | ||
| Enable Voltage, EN | EN | -0.3 | 65 | V | 10 | ||
| Switch Voltage, SW | SW | -0.6 | 65 | V | 10 | ||
| Switch Voltage, SW (transient) | SW | -5 | 70 | V | t ≤ 100ns | 10 | |
| Power Good Voltage, PGOOD | PGOOD | -0.3 | 65 | V | 10 | ||
| BOOT to SW voltage | BOOT−SW | -0.3 | 6 | V | 10 | ||
| All Other Pins voltage | -0.3 | 6 | V | All other pins | 10 | ||
| Lead Temperature (Soldering, 10 sec.) | 260 | °C | 10 sec soldering | 10 | |||
| Junction Temperature | TJ | 150 | °C | 10 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 10 | ||
| Supply Input Voltage, VIN | VIN | 4 | 60 | V | 10 | ||
| Output Voltage | VOUT | 0.8 | V | Upper limit printed as VIN | 10 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 10 | ||
| Input Operating Voltage | VIN | 4 | 60 | V | After soft-start is finished | 11 | |
| VIN Under-Voltage Lockout Threshold (rising) | VUVLOH | 4.1 | 4.3 | 4.5 | V | VIN rising | 11 |
| VIN Under-Voltage Lockout Threshold (falling) | VUVLOL | 3.8 | 3.9 | 4 | V | VIN falling | 11 |
| Shutdown Current | ISHDN | 2.25 | 5 | μA | VEN = 0V | 11 | |
| Quiescent Current | IQ | 100 | 135 | μA | VEN = 2V, VFB = 0.83V, not switching | 11 | |
| Enable Threshold Voltage | VTH_EN | 1.1 | 1.2 | 1.3 | V | 11 | |
| Pull-Up Current (VTH_EN − 50mV) | IEN | 0.58 | 1.2 | 1.8 | μA | VTH_EN − 50mV | 11 |
| Hysteresis Current | IEN_Hys | 2.2 | 3.4 | 4.5 | μA | 11 | |
| Reference Voltage | VREF | 0.792 | 0.8 | 0.808 | V | 11 | |
| High-Side Switch On-Resistance | RDS(ON)_H | 80 | 150 | mΩ | VIN = 12V, VBOOT − VSW = 5V | 11 | |
| Current Limit | ILIM | 4.675 | 5.5 | 6.325 | A | fSW = 500kHz, VOUT = 5V | 11 |
| Minimum On-Time | tON_MIN | 135 | ns | IOUT = 1A | 12 | ||
| Switching Frequency 1 | fSW1 | 90 | 105 | 120 | kHz | RRT/SYNC = 1M | 12 |
| Switching Frequency 2 | fSW2 | 450 | 500 | 550 | kHz | RRT/SYNC = 200k | 12 |
| Switching Frequency 3 | fSW3 | 2200 | 2450 | 2700 | kHz | RRT/SYNC = 37.4k | 12 |
| SYNC Frequency Range | 0.3 | 2.2 | MHz | External clock | 12 | ||
| Minimum Sync Pulse Width | 20 | ns | 12 | ||||
| SYNC Threshold Voltage (high) | VIH_SYNC | 1.55 | 2 | V | 12 | ||
| SYNC Threshold Voltage (low) | VIL_SYNC | 0.5 | 1.2 | V | 12 | ||
| Soft-Start Period | 1.4 | 2 | 2.6 | ms | 10% to 90%, RT6363GSP | 12 | |
| Thermal Resistance, Junction-to-ambient (JEDEC standard) | θJA | 30.4 | °C/W | SOP-8 (Exposed pad) column | 10 | ||
| Thermal Resistance, Junction-to-case (top) | θJC(Top) | 73.9 | °C/W | SOP-8 (Exposed pad) column | 10 | ||
| Thermal Resistance, Junction-to-case (bottom) | θJC(Bottom) | 3.4 | °C/W | SOP-8 (Exposed pad) column | 10 | ||
| Thermal Resistance, Junction-to-ambient (specific EVB) | θJA(EVB) | 30 | °C/W | SOP-8 (Exposed pad) column | 10 | ||
| Junction-to-top characterization parameter | ψJT | 5 | °C/W | SOP-8 (Exposed pad) column | 10 | ||
| Junction-to-board characterization parameter | ψJB | 13.2 | °C/W | SOP-8 (Exposed pad) column | 10 |
CAD (KiCad official)
- Symbol:
RT6363GSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
rt6363gsp-etched.step/rt6363gsp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt6363gsp.step/rt6363gsp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (35 pp, sha256
ec0b54727fbce6c7, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).