# RT6283BGSP

**Richtek Tech** · DC-DC Converters · SOP-8-EP

RT6283BGSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switch node connected to the external L-C filter. |
| 2 | BOOT | passive | Bootstrap supply for high-side gate drive; a 100nF or greater capacitor is recommended from BOOT to SW. |
| 3 | EN | input | Enable control input: logic-high enables the converter and logic-low (below 0.4V) forces shutdown mode. |
| 4 | GND | power_in | Ground pin, tied to the same GND net as the exposed pad. |
| 5 | FB | input | Feedback input connected to the converter output through a resistive divider, regulating to the 0.8V reference. |
| 6 | COMP | passive | Compensation node; connect a series RC network from COMP to GND, with an additional capacitor to GND in some cases. |
| 7 | RLIM | passive | Current limit setting; a resistor connected here sets the upper switch current limit (1.9A to 7A range). |
| 8 | VIN | power_in | Power input with a 4.5V to 30V range that must be bypassed with a suitable large ceramic capacitor. |
| 9 | GND | power_in | Exposed thermal pad, which must be soldered to a large PCB and connected to GND for maximum thermal dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Supply Chip |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown Supply Current |  |  | 0.5 | 3 | μA | VEN = 0V | 4 |
| Quiescent Current | IQ |  | 0.9 | 1.2 | mA | VEN = 3V, VFB = 0.9V | 4 |
| Feedback Reference Voltage | VREF | 0.788 | 0.8 | 0.812 | V | 4.5V ≤ VIN ≤ 30V | 4 |
| High Side Switch Leakage Current |  |  | 0 | 10 | μA | VEN = 0V, VSW = 0V | 4 |
| Upper Switch Current Limit Range | UOC | 1.9 |  | 7 | A |  | 4 |
| Upper Switch Current Limit | UOC | 1.9 | 2.5 | 3.1 | A | Min. Duty Cycle, RLIM = 57.6k (Note 5) | 4 |
| Upper Switch Current Limit | UOC | 2.7 | 3.5 | 4.2 | A | Min. Duty Cycle, RLIM = 84.5k (Note 5) | 4 |
| Upper Switch Current Limit | UOC | 4.5 | 5.5 | 6.5 | A | Min. Duty Cycle, RLIM = 137k (Note 5) | 4 |
| Oscillation Frequency | fOSC1 | 450 | 500 | 550 | kHz |  | 5 |
| EN Input Voltage Logic-High | VIH | 2 |  |  | V |  | 5 |
| EN Input Voltage Logic-Low | VIL |  |  | 0.4 | V |  | 5 |
| Input Under Voltage Lockout Threshold | VUVLO | 3.9 | 4.1 | 4.3 | V | VIN Rising | 5 |
| Load Regulation | VLOAD |  |  | 0.05 | %/A |  | 5 |
| Line Regulation | VLINE |  |  | 0.1 | % | VIN = 4.5V to 30V | 5 |
| Supply Input Voltage (Absolute Maximum) | VIN | -0.3 |  | 40 | V |  | 4 |
| Switch Voltage |  | -0.3 |  |  | V | Max = VIN + 0.3V | 4 |
| VBOOT − VSW | VBOOT − VSW | -0.3 |  | 6 | V |  | 4 |
| Other Pins Voltage |  | -0.3 |  | 40 | V |  | 4 |
| Power Dissipation | PD |  |  | 2.041 | W | TA = 25°C, SOP-8 (Exposed Pad) | 4 |
| Package Thermal Resistance, junction to ambient | θJA |  | 49 |  | °C/W | SOP-8 (Exposed Pad), JEDEC 51-7 four-layer board, natural convection, TA = 25°C (Note 2) | 4 |
| Package Thermal Resistance, junction to case | θJC |  | 15 |  | °C/W | SOP-8 (Exposed Pad), measured at exposed pad (Note 2) | 4 |
| Thermal Resistance, junction to ambient | θJA |  | 75 |  | °C/W | Copper area (2.3 x 2.3) mm2, min. copper PCB layout | 13 |
| Thermal Resistance, junction to ambient | θJA |  | 64 |  | °C/W | Copper area 10mm2 | 13 |
| Thermal Resistance, junction to ambient | θJA |  | 54 |  | °C/W | Copper area 30mm2 | 13 |
| Thermal Resistance, junction to ambient | θJA |  | 51 |  | °C/W | Copper area 50mm2 | 13 |
| Lead Temperature (Soldering) |  |  |  | 260 | °C | Soldering, 10 sec. | 4 |
| Junction Temperature | TJ |  |  | 150 | °C |  | 4 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 4 |
| ESD Susceptibility |  |  |  | 2 | kV | HBM (Human Body Model) | 4 |
| Supply Input Voltage (Recommended) | VIN | 4.5 |  | 30 | V |  | 4 |
| Junction Temperature Range | TJ | -40 |  | 125 | °C |  | 4 |
| Ambient Temperature Range | TA | -40 |  | 85 | °C |  | 4 |

## CAD (KiCad official)

- Symbol: `RT6283BGSP`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `rt6283bgsp-etched.step` / `rt6283bgsp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt6283bgsp.step` / `rt6283bgsp.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Richtek Tech datasheet](docs/rt6283bgsp-datasheet.pdf) (16 pp, sha256 `b1bd133bbafcc43a`, retrieved 2026-10-21, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/rt6283bgsp-datasheet.pdf)