component
RT6263BHGJ8F
Public Made by Adomby adom
Richtek Tech DC-DC Converters, TSOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 16d ago |
| viewers | 16d ago |
| package.json | 16d ago |
| page.json | 16d ago |
| README.md | 16d ago |
| rt6263bhgj8f-etched.glb | 16d ago |
| rt6263bhgj8f-etched.step | 16d ago |
| rt6263bhgj8f-hero.glb | 16d ago |
| rt6263bhgj8f-hero.overlay.json | 16d ago |
| rt6263bhgj8f.glb | 16d ago |
| rt6263bhgj8f.kicad_mod | 16d ago |
| rt6263bhgj8f.kicad_sym | 16d ago |
| rt6263bhgj8f.lbr | 16d ago |
| rt6263bhgj8f.step | 16d ago |
RT6263BHGJ8F
Richtek Tech · DC-DC Converters · TSOT-23-8
RT6263BHGJ8F from Richtek Tech, in a TSOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Power ground for the device, to which the input bypass capacitors must connect together with the VIN pin. |
| 2 | SW | output | Switch node between the internal switch and the synchronous rectifier, connected to the inductor and the bootstrap capacitor. |
| 3 | VIN | power_in | Power input with a supply range of 4.5V to 17V, with input bypass capacitors connected directly to this pin and the GND pins. |
| 4 | PGOOD | output | Open-drain power-good indication output that is pulled low to GND if any internal protection is triggered during start-up. |
| 5 | SS | passive | Soft-start capacitor connection node that sets the soft-start time when a capacitor (8.2nF suggested) is connected to GND and must not be left unconnected. |
| 6 | FB | input | Feedback voltage input that connects to the midpoint of the external feedback divider, with the device regulating FB to the feedback reference voltage. |
| 7 | EN | input | Enable control input where a logic high enables the device and connecting it to GND disables the device. |
| 8 | BOOT | power_out | Bootstrap capacitor connection node that supplies the high-side gate driver and connects to the SW pin through a ceramic capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | TSOT-23-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Input Operating Voltage | VIN | 4.5 | 17 | V | 9 | ||
| Under-Voltage Lockout Threshold | VUVLO | 3.7 | 4 | 4.3 | V | 9 | |
| Shutdown Current | ISHDN | 3 | 10 | µA | VEN = 0V | 9 | |
| Quiescent Current | IQ | 180 | 280 | µA | VEN = 2V, VFB = 0.8V | 9 | |
| Enable Voltage Threshold (high-level input) | VEN_H | 1.16 | 1.25 | 1.34 | V | EN high-level input voltage | 9 |
| Enable Voltage Threshold (low-level input) | VEN_L | 1.01 | 1.1 | 1.19 | V | EN low-level input voltage | 9 |
| EN Pin Pull-Down Resistance | REN_DN | 225 | 450 | 900 | k | VEN = 12V | 9 |
| Feedback Threshold Voltage | VFB | 758 | 765 | 772 | mV | VOUT = 1.05V | 9 |
| Feedback Input Current | IFB | 0.1 | 0 | 0.1 | A | VFB = 0.8V, TA = 25°C | 9 |
| Discharge Resistance | RDISCHG | 100 | 200 | VEN = 0V, VSW = 1V | 9 | ||
| Low-Side Switch Valley Current Limit | ILIM_L | 3.3 | 4.2 | A | 9 | ||
| Minimum Off-Time | tOFF_MIN | 200 | 260 | ns | VFB = 0.5V | 9 | |
| Power Good Threshold (rising, low to high) | VTH_PGLH | 85 | 90 | 95 | % | VFB rising, PGOOD from low to high | 10 |
| Power Good Sink Current | IPGOOD | 0.5 | 1 | mA | VPGOOD = 0.5V | 10 | |
| Supply Input Voltage (absolute maximum) | VIN | -0.3 | 20 | V | 8 | ||
| Enable Voltage (absolute maximum) | -0.3 | 20 | V | 8 | |||
| Switch Voltage (absolute maximum) | -0.3 | 20.3 | V | 8 | |||
| Switch Voltage transient (absolute maximum) | -5 | 25 | V | <100ns | 8 | ||
| BOOT Voltage (absolute maximum) | -0.3 | 26 | V | 8 | |||
| BOOT to SW Voltage (absolute maximum) | VBOOT - VSW | -0.3 | 6 | V | 8 | ||
| Other Pins Voltage (absolute maximum) | -0.3 | 6 | V | 8 | |||
| Lead Temperature (Soldering, 10 sec.) | 260 | °C | Soldering, 10 sec. | 8 | |||
| Junction Temperature (absolute maximum) | 150 | °C | 8 | ||||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Power Dissipation TSOT-23-8 (FC) | PD | 1.6 | W | TA = 25°C | 8 | ||
| Supply Input Voltage (recommended) | 4.5 | 17 | V | 8 | |||
| Junction Temperature Range (recommended) | -40 | 125 | °C | 8 | |||
| Junction-to-ambient thermal resistance (JEDEC standard) | θJA | 86 | °C/W | JEDEC standard | 8 | ||
| Junction-to-case (top) thermal resistance | θJC(Top) | 108.2 | °C/W | 8 | |||
| Junction-to-case (bottom) thermal resistance | θJC(Bottom) | 5 | °C/W | 8 | |||
| Junction-to-ambient thermal resistance (specific EVB) | θJA(EVB) | 62.5 | °C/W | specific EVB | 8 | ||
| Junction-to-top characterization parameter | ΨJC(Top) | 11.21 | °C/W | 8 | |||
| Junction-to-board characterization parameter | ΨJB | 33.64 | °C/W | 8 |
CAD (KiCad official)
- Symbol:
RT6263BHGJ8F - Footprint:
Package_TO_SOT_SMD:TSOT-23-8 - 3D model: TSOT-23-8 (KiCad packages3D, STEP)
- 3D model files:
rt6263bhgj8f-etched.step/rt6263bhgj8f-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt6263bhgj8f.step/rt6263bhgj8f.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (27 pp, sha256
d81e60822e0d115c, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).