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RT6252AHGJ6F
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RICHTEK(立锜) DC-DC Converters, TSOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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RT6252AHGJ6F
RICHTEK(立锜) · DC-DC Converters · TSOT-23-6
RT6252AHGJ6F from RICHTEK(立锜), in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Power ground for the converter. |
| 2 | SW | output | Switch node between the internal high-side switch and the synchronous rectifier; connect to the inductor and the bootstrap capacitor. |
| 3 | VIN | power_in | Power input with a stated input range of 4.5V to 17V; connect input bypass capacitors directly to this pin and the GND pins, with an MLCC above 20µF recommended. |
| 4 | FB | input | Feedback voltage input connected to the midpoint of the output resistive divider; the device regulates FB to the feedback reference, typically 0.765V. |
| 5 | EN | input | Enable control input: a logic-high level enables the device and connecting it to GND disables the device. |
| 6 | BOOT | passive | Bootstrap capacitor connection that supplies the high-side gate driver; connect a 0.1µF ceramic capacitor between this pin and SW. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RICHTEK(立锜) |
| Package | TSOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Input Operating Voltage | VIN | 4.5 | 17 | V | 8 | ||
| Under-Voltage Lockout Threshold | VUVLO | 3.7 | 4 | 4.3 | V | 8 | |
| Shutdown Current | ISHDN | 4 | µA | VEN = 0V | 8 | ||
| Enable Voltage Threshold, EN high-level input voltage | VEN_H | 1.16 | 1.25 | 1.34 | V | 8 | |
| Enable Voltage Threshold, EN low-level input voltage | VEN_L | 1.01 | 1.1 | 1.19 | V | 8 | |
| EN Pin Pull-Down Resistance | REN_DN | 225 | 450 | 900 | k | EN pin resistance to GND, VEN = 12V | 8 |
| Feedback Threshold Voltage | VFB | 758 | 765 | 772 | mV | VOUT = 1.05V | 8 |
| Feedback Input Current | IFB | 0.1 | 0 | 0.1 | µA | VFB = 0.8V, TA = 25°C | 8 |
| Low-Side Switch Valley Current Limit | ILIM_L | 2.2 | 3.2 | 4.2 | A | 8 | |
| Minimum Off-Time | tOFF_MIN | 200 | 260 | ns | VFB = 0.5V | 8 | |
| Supply Voltage, Absolute Maximum | VIN | -0.3 | 20 | V | 7 | ||
| Enable Voltage, EN | -0.3 | 20 | V | 7 | |||
| Switch Voltage, SW | -0.3 | 20.3 | V | 7 | |||
| Switch Voltage, SW transient | -5 | 25 | V | < 100ns | 7 | ||
| BOOT Voltage | -0.3 | 26 | V | 7 | |||
| BOOT to SW Voltage | VBOOT, VSW | -0.3 | 6 | V | 7 | ||
| Feedback Voltage, FB | -0.3 | 6 | V | 7 | |||
| Lead Temperature (Soldering) | 260 | °C | Soldering, 10 sec. | 7 | |||
| Junction Temperature | 150 | °C | 7 | ||||
| Storage Temperature Range | -65 | 150 | °C | 7 | |||
| Supply Input Voltage | 4.5 | 17 | V | 7 | |||
| Junction Temperature Range | -40 | 125 | °C | 7 | |||
| Junction-to-ambient thermal resistance (JEDEC standard) | θJA | 88.7 | °C/W | JEDEC standard | 7 | ||
| Junction-to-case (top) thermal resistance | θJC(Top) | 76.9 | °C/W | 7 | |||
| Junction-to-case (bottom) thermal resistance | θJC(Bottom) | 6 | °C/W | 7 | |||
| Junction-to-ambient thermal resistance (specific EVB) | θJA(EVB) | 63.3 | °C/W | specific EVB | 7 | ||
| Junction-to-top characterization parameter | ΨJC(Top) | 15.3 | °C/W | 7 | |||
| Junction-to-board characterization parameter | ΨJB | 34.66 | °C/W | 7 |
CAD (KiCad official)
- Symbol:
RT6252AHGJ6F - Footprint:
Package_TO_SOT_SMD:TSOT-23-6 - 3D model: TSOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
rt6252ahgj6f-etched.step/rt6252ahgj6f-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt6252ahgj6f.step/rt6252ahgj6f.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RICHTEK(立锜) datasheet (31 pp, sha256
b3073e6d0c76ec40, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# RT6252AHGJ6F
**RICHTEK(立锜)** · DC-DC Converters · TSOT-23-6
RT6252AHGJ6F from RICHTEK(立锜), in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Power ground for the converter. |
| 2 | SW | output | Switch node between the internal high-side switch and the synchronous rectifier; connect to the inductor and the bootstrap capacitor. |
| 3 | VIN | power_in | Power input with a stated input range of 4.5V to 17V; connect input bypass capacitors directly to this pin and the GND pins, with an MLCC above 20µF recommended. |
| 4 | FB | input | Feedback voltage input connected to the midpoint of the output resistive divider; the device regulates FB to the feedback reference, typically 0.765V. |
| 5 | EN | input | Enable control input: a logic-high level enables the device and connecting it to GND disables the device. |
| 6 | BOOT | passive | Bootstrap capacitor connection that supplies the high-side gate driver; connect a 0.1µF ceramic capacitor between this pin and SW. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RICHTEK(立锜) |
| Package | TSOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Input Operating Voltage | VIN | 4.5 | | 17 | V | | 8 |
| Under-Voltage Lockout Threshold | VUVLO | 3.7 | 4 | 4.3 | V | | 8 |
| Shutdown Current | ISHDN | | | 4 | µA | VEN = 0V | 8 |
| Enable Voltage Threshold, EN high-level input voltage | VEN_H | 1.16 | 1.25 | 1.34 | V | | 8 |
| Enable Voltage Threshold, EN low-level input voltage | VEN_L | 1.01 | 1.1 | 1.19 | V | | 8 |
| EN Pin Pull-Down Resistance | REN_DN | 225 | 450 | 900 | k | EN pin resistance to GND, VEN = 12V | 8 |
| Feedback Threshold Voltage | VFB | 758 | 765 | 772 | mV | VOUT = 1.05V | 8 |
| Feedback Input Current | IFB | 0.1 | 0 | 0.1 | µA | VFB = 0.8V, TA = 25°C | 8 |
| Low-Side Switch Valley Current Limit | ILIM_L | 2.2 | 3.2 | 4.2 | A | | 8 |
| Minimum Off-Time | tOFF_MIN | | 200 | 260 | ns | VFB = 0.5V | 8 |
| Supply Voltage, Absolute Maximum | VIN | -0.3 | | 20 | V | | 7 |
| Enable Voltage, EN | | -0.3 | | 20 | V | | 7 |
| Switch Voltage, SW | | -0.3 | | 20.3 | V | | 7 |
| Switch Voltage, SW transient | | -5 | | 25 | V | < 100ns | 7 |
| BOOT Voltage | | -0.3 | | 26 | V | | 7 |
| BOOT to SW Voltage | VBOOT, VSW | -0.3 | | 6 | V | | 7 |
| Feedback Voltage, FB | | -0.3 | | 6 | V | | 7 |
| Lead Temperature (Soldering) | | | | 260 | °C | Soldering, 10 sec. | 7 |
| Junction Temperature | | | | 150 | °C | | 7 |
| Storage Temperature Range | | -65 | | 150 | °C | | 7 |
| Supply Input Voltage | | 4.5 | | 17 | V | | 7 |
| Junction Temperature Range | | -40 | | 125 | °C | | 7 |
| Junction-to-ambient thermal resistance (JEDEC standard) | θJA | | 88.7 | | °C/W | JEDEC standard | 7 |
| Junction-to-case (top) thermal resistance | θJC(Top) | | 76.9 | | °C/W | | 7 |
| Junction-to-case (bottom) thermal resistance | θJC(Bottom) | | 6 | | °C/W | | 7 |
| Junction-to-ambient thermal resistance (specific EVB) | θJA(EVB) | | 63.3 | | °C/W | specific EVB | 7 |
| Junction-to-top characterization parameter | ΨJC(Top) | | 15.3 | | °C/W | | 7 |
| Junction-to-board characterization parameter | ΨJB | | 34.66 | | °C/W | | 7 |
## CAD (KiCad official)
- Symbol: `RT6252AHGJ6F`
- Footprint: `Package_TO_SOT_SMD:TSOT-23-6`
- 3D model: TSOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `rt6252ahgj6f-etched.step` / `rt6252ahgj6f-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt6252ahgj6f.step` / `rt6252ahgj6f.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [RICHTEK(立锜) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603052372176891904) (31 pp, sha256 `b3073e6d0c76ec40`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/rt6252ahgj6f-datasheet.pdf)