# RT6206BHGSP

**Richtek Tech** · DC-DC Converters · SOP-8-EP

RT6206BHGSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable control input: logic-high (above 2V, up to 18V) enables the converter and logic-low (below 0.4V) shuts it down, reducing quiescent supply current to below 10µA. |
| 2 | FB | input | Feedback voltage input that regulates the output through an external resistive divider, with a feedback threshold of 0.765V typical. |
| 3 | VREG5 | power_out | Internal regulator output that supplies the control circuit (5.1V typical, 4.8V to 5.4V); connect a 1µF capacitor to GND to stabilize it. |
| 4 | SS | passive | Soft-start time setting: an external capacitor between SS and GND sets the soft-start time, with a 6µA charge current on the capacitor. |
| 5 | PGND | power_in | Power ground for the converter; connect to the exposed pad and to the system ground plane. |
| 6 | SW | output | Switch node; connect this pin to an external L-C output filter, keeping the trace wide and short. |
| 7 | BOOT | passive | Bootstrap supply for the high-side gate driver; connect a 0.1µF capacitor between BOOT and SW. |
| 8 | VIN | power_in | Power input with a range of 4.5V to 18V; must be bypassed with a suitably large (10µF x 2) ceramic capacitor. |
| 9 | PGND | power_in | Exposed thermal pad, which is power ground; it must be soldered to a large PCB and connected to PGND for maximum power dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage, VIN | VIN | 4.5 |  | 18 | V |  | 5 |
| Junction Temperature Range |  | -40 |  | 125 | °C |  | 5 |
| Ambient Temperature Range |  | -40 |  | 85 | °C |  | 5 |
| Supply Voltage, VIN, VINR |  | -0.3 |  | 20 | V |  | 5 |
| Switch Voltage, SW |  | -0.3 |  |  | V | upper limit printed as VIN + 0.3V | 5 |
| Switch Voltage, SW (< 10ns) |  | -5 |  | 25 | V | < 10ns | 5 |
| BOOT to SW |  | -0.3 |  | 6 | V |  | 5 |
| EN, VOUT |  | -0.3 |  | 20 | V |  | 5 |
| Other Pins |  | -0.3 |  | 6 | V |  | 5 |
| Power Dissipation, PD | PD |  |  | 2.041 | W | TA = 25°C, SOP-8 (Exposed Pad) | 5 |
| Junction Temperature Range (absolute maximum) |  |  |  | 150 | °C |  | 5 |
| Lead Temperature (Soldering, 10 sec.) |  |  |  | 260 | °C | soldering, 10 sec | 5 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 5 |
| ESD Susceptibility, HBM |  |  |  | 2 | kV | Human Body Model | 5 |
| Shutdown Current | ISHDN |  | 1 | 10 | μA | VEN = 0V | 5 |
| Quiescent Current | IQ |  | 1 | 1.3 | mA | VEN = 5V, VFB = 0.8V | 5 |
| EN Input Voltage Logic-High |  | 2 |  | 18 | V |  | 5 |
| EN Input Voltage Logic-Low |  |  |  | 0.4 | V |  | 5 |
| Feedback Threshold Voltage | VFB | 0.757 | 0.765 | 0.773 | V | TA = 25°C | 5 |
| Feedback Threshold Voltage | VFB | 0.755 |  | 0.775 | V | TA = -40°C to 85°C | 5 |
| Feedback Input Current | IFB |  | 0.01 | 0.1 | μA | VFB = 0.8V | 5 |
| VREG5 Output Voltage | VREG5 | 4.8 | 5.1 | 5.4 | V | 6V ≤ VIN ≤ 18V, 0 < IVREG5 ≤ 5mA | 5 |
| Line Regulation |  |  |  | 20 | mV | 6V ≤ VIN ≤ 18V, IVREG5 = 5mA | 6 |
| Load Regulation |  |  |  | 100 | mV | 0 ≤ IVREG5 ≤ 5mA | 6 |
| Current Limit | ILIM | 5.8 | 6.9 | 8.4 | A |  | 6 |
| SS Charge Current |  | 4 | 6 | 8 | μA | VSS = 0V | 6 |
| UVLO Threshold Wake up |  | 3.6 | 3.85 | 4.1 | V | VREG5 | 6 |
| UVLO Hysteresis |  | 0.16 | 0.35 | 0.47 | V |  | 6 |
| OVP Trip Threshold |  | 115 | 120 | 125 | % | OVP detect | 6 |
| UVP Trip Threshold |  | 65 | 70 | 75 | % |  | 6 |
| Minimum Off-Time | tOFF(MIN) |  | 260 | 310 | ns | VFB = 0.7V | 6 |
| Junction-to-Ambient Thermal Resistance, SOP-8 (Exposed Pad) | θJA |  | 49 |  | °C/W | four-layer JEDEC 51-7 test board | 5 |
| Junction-to-Case Thermal Resistance, SOP-8 (Exposed Pad) | θJC |  | 15 |  | °C/W | measured at exposed pad | 5 |
| Output Current, IVREG5 | IVREG5 |  | 70 |  | mA | VIN = 6V, VREG5 = 4V, TA = 25C | 6 |
| High-Side Switch On Resistance | RDS(ON)_H |  | 80 |  | mΩ | (VBOOT − VSW) = 5.5V | 6 |
| Low-Side Switch On Resistance | RDS(ON)_L |  | 35 |  | mΩ |  | 6 |
| Thermal Shutdown Threshold | TSD |  | 150 |  | °C | Shutdown temperature | 6 |
| Thermal Shutdown Hysteresis | TSD |  | 20 |  | °C |  | 6 |
| On-Time | tON |  | 135 |  | ns | VOUT = 1.05V | 6 |
| SS Discharge Current (Hiccup Mode) |  |  | 0.5 |  | A | VSS = 0.5V (Hiccup Mode) | 6 |
| OVP Prop Delay |  |  | 5 |  | μs |  | 6 |
| UVP Hysteresis |  |  | 10 |  | % |  | 6 |
| UVP Prop Delay |  |  | 250 |  | μs |  | 6 |

## CAD (KiCad official)

- Symbol: `RT6206BHGSP`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `rt6206bhgsp-etched.step` / `rt6206bhgsp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt6206bhgsp.step` / `rt6206bhgsp.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Richtek Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884271376949248) (18 pp, sha256 `c74e2910fe679186`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/rt6206bhgsp-datasheet.pdf)