# RT5797ALGQW

**Richtek Tech** · DC-DC Converters · DFN-8-EP(2x2)

RT5797ALGQW from Richtek Tech, in a DFN-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback voltage input; an external resistor divider from the output to GND, tapped to this pin, sets the output voltage, with a 0.6V reference (VREF 0.594V to 0.606V). |
| 2 | PG | output | Power good open-drain output that needs an external pull-up resistor; it is pulled up when FB is within 90% of the reference and otherwise LOW. |
| 3 | VIN | power_in | Supply voltage input; the RT5797A operates from 2.7V to 6V (absolute maximum supply 6.5V). |
| 4 | PGND | power_in | Power ground; the exposed pad (pin 9) must be soldered to a large PCB and connected to PGND for maximum power dissipation. |
| 5 | NC | unconnected | No internal connection. |
| 6 | LX | output | Switch node connecting the internal high-side and low-side power MOSFETs to the external inductor; absolute maximum is 0.3V to (VIN + 0.3V), with <20ns transients to 4.5V to 7.5V. |
| 7 | EN | input | Enable control input; a logic-high enables the converter and a logic-low forces shutdown mode (EN below 400mV keeps the part in shutdown). |
| 8 | SGND | power_in | Signal ground for the control circuitry. |
| 9 | PGND | power_in | Exposed pad, power ground; must be soldered to a large PCB and connected to PGND for maximum power dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | DFN-8-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Input Voltage (absolute max) |  | -0.3 |  | 6.5 | V |  | 5 |
| LX Pin Switch Voltage |  | -0.3 |  |  | V | max printed as VIN + 0.3V | 5 |
| LX Pin Switch Voltage (transient) |  | -4.5 |  | 7.5 | V | <20ns | 5 |
| Junction Temperature (absolute max) |  | -40 |  | 150 | °C |  | 5 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 5 |
| Lead Temperature (soldering) |  |  |  | 260 | °C | 10 sec soldering | 5 |
| ESD Susceptibility HBM |  |  |  | 2 | kV | HBM (Human Body Model) | 5 |
| Power Dissipation WDFN-8L 2x2 | PD |  |  | 2.19 | W | TA = 25°C | 5 |
| Supply Input Voltage (recommended) |  | 2.7 |  | 6 | V |  | 5 |
| Ambient Temperature Range (recommended) |  | -40 |  | 85 | °C |  | 5 |
| Junction Temperature Range (recommended) |  | -40 |  | 125 | °C |  | 5 |
| Input Voltage | VIN | 2.7 |  | 6 | V |  | 5 |
| Feedback Reference Voltage | VREF | 0.594 | 0.6 | 0.606 | V |  | 5 |
| Feedback Leakage Current | IFB |  |  | 0.1 | A | VFB = 0.6V | 5 |
| DC Bias Current (Active) |  |  | 22 | 36 | A | VFB = 0.63V, not switching | 5 |
| DC Bias Current (Shutdown) |  |  |  | 1 | A |  | 5 |
| Switching Leakage Current |  |  |  | 1 | A |  | 5 |
| Switching Frequency |  | 0.8 | 1 | 1.2 | MHz |  | 5 |
| Switch On Resistance, Low | RNMOS |  | 70 | 85 | m | ISW = 0.3A | 5 |
| Switch On Resistance, High | RPMOS |  | 100 | 125 | m | ISW = 0.3A | 5 |
| Valley Current Limit | ILIM | 3.03 | 3.7 | 4.6 | A |  | 5 |
| Under-Voltage Lockout Threshold (rising) | VUVLO |  | 2.25 | 2.5 | V | VDD rising | 5 |
| Enable Threshold Voltage H-Level | VENH | 0.7 | 0.85 | 1.05 | V | EN rising | 6 |
| Enable Threshold Voltage L-Level | VENL | 0.5 | 0.75 | 0.95 | V | EN falling | 6 |
| PG Pin Threshold (relative to VOUT) |  | 85 | 90 | 95 | % | Rising | 6 |
| PG Pin Threshold (relative to VOUT) |  | 80 | 85 | 90 | % | Falling | 6 |
| PG Open-Drain Impedance |  |  |  | 20 |  | PG = low | 6 |
| Soft-Start Time | tSS | 0.5 | 1.2 | 2 | ms |  | 6 |
| Minimum Off Time | tOFF_MIN | 70 | 120 | 180 | ns |  | 6 |
| Maximum Duty Cycle | DMAX | 70 |  |  | % | (Note 5) | 6 |
| Output Discharge Switch On Resistance |  | 1.2 | 1.8 | 2.4 | k |  | 6 |
| Over-Voltage Protection (relative to VOUT) | VOVP | 115 | 120 | 125 | % | Rising | 6 |
| Package Thermal Resistance, Junction-to-Ambient (WDFN-8L 2x2) | JA |  | 45.5 |  | °C/W | Natural convection, TA = 25°C, JEDEC 51-7 four-layer board (Note 2) | 5 |

## CAD (KiCad official)

- Symbol: `RT5797ALGQW`
- Footprint: `Package_DFN_QFN:DFN-8-1EP_2x2mm_P0.5mm_EP0.6x1.2mm`
- 3D model: DFN-8-EP(2x2) (KiCad packages3D, STEP)
- 3D model files: `rt5797algqw-etched.step` / `rt5797algqw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `rt5797algqw.step` / `rt5797algqw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Richtek Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590226658789007360) (17 pp, sha256 `0ebe371e02364fc5`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/rt5797algqw-datasheet.pdf)