component
RT2862AGSP
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 17d ago |
| viewers | 17d ago |
| package.json | 17d ago |
| page.json | 17d ago |
| README.md | 17d ago |
| rt2862agsp-etched.glb | 17d ago |
| rt2862agsp-etched.step | 17d ago |
| rt2862agsp-hero.glb | 17d ago |
| rt2862agsp-hero.overlay.json | 17d ago |
| rt2862agsp.glb | 17d ago |
| rt2862agsp.kicad_mod | 17d ago |
| rt2862agsp.kicad_sym | 17d ago |
| rt2862agsp.lbr | 17d ago |
| rt2862agsp.step | 17d ago |
RT2862AGSP
Richtek Tech · DC-DC Converters · SOP-8-EP
RT2862AGSP from Richtek Tech, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switch node, which must be connected to the external L-C filter. |
| 2 | BOOT | power_out | Bootstrap supply for the high-side MOSFET; a 100nF or greater capacitor must be connected between BOOT and SW. |
| 3 | EN | input | Enable control input: the converter is enabled when EN is above 2V and enters shutdown when EN is below 0.4V. |
| 4 | GND | power_in | Ground pin; the GND net must be connected to the exposed pad (pin 9) and the exposed pad must be soldered to a large PCB for maximum thermal dissipation. |
| 5 | FB | input | Feedback voltage input that sets the output voltage through an external resistive divider, regulating to the 0.8V reference (0.784V to 0.816V). |
| 6 | COMP | passive | Compensation node for the control loop; connect an R-C network from COMP to GND, with an additional capacitor from COMP to GND in some cases. |
| 7 | RT | passive | Switching frequency setting; an external resistor sets the switching frequency from 300kHz to 1MHz. |
| 8 | VIN | power_in | Power input with a range of 4.5V to 36V, which must be bypassed with a suitable large ceramic capacitor. |
| 9 | GND | power_in | Exposed thermal pad connected to GND; it must be soldered to a large PCB and connected to GND for maximum thermal dissipation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown Supply Current | 10 | A | VEN = 0V | 4 | |||
| Quiescent Current | IQ | 1 | 1.3 | mA | VEN = 3V, VFB = 0.9V | 4 | |
| Feedback Reference Voltage | VREF | 0.784 | 0.8 | 0.816 | V | 4.5V ≤ VIN ≤ 36V | 4 |
| High-Side Switch On-Resistance | RDS(ON)1 | 105 | 190 | mΩ | 4 | ||
| Low-Side Switch On-Resistance | RDS(ON)2 | 80 | 145 | mΩ | 4 | ||
| High-Side Switch Current Limit Range | UOC | 4.25 | 5 | 5.75 | A | 4 | |
| Oscillation Frequency | fOSC1 | 264 | 300 | 336 | kHz | RT = 191k | 4 |
| Oscillation Frequency | fOSC1 | 440 | 500 | 560 | kHz | RT = 113k | 4 |
| Oscillation Frequency | fOSC1 | 880 | 1000 | 1120 | kHz | RT = 51k | 4 |
| Minimum On-Time | tON | 100 | 120 | ns | 4 | ||
| EN Input Voltage Logic-High | VIH | 2 | 3.3 | V | 5 | ||
| EN Input Voltage Logic-Low | VIL | 0.4 | V | 5 | |||
| Input Under-Voltage Lockout Threshold | VUVLO | 3.7 | 4.2 | 4.5 | V | VIN Rising | 5 |
| Supply Voltage | VIN | -0.3 | 40 | V | 4 | ||
| Switch Voltage | SW | -0.3 | V | Maximum printed as (VIN + 0.3V) | 4 | ||
| BOOT Pin Voltage | BOOT | -0.3 | 46.3 | V | 4 | ||
| EN Pin Voltage | EN | -0.3 | 40 | V | With REN (150kΩ to 600kΩ) to VIN | 4 | |
| SW Voltage (transient) | SW | -5 | 46.3 | V | t < 10ns | 4 | |
| EN Pin Voltage | EN | -0.3 | 3.6 | V | 4 | ||
| Other Pins Voltage | -0.3 | 40 | V | 4 | |||
| Power Dissipation SOP-8 (Exposed Pad) | PD | 2.041 | W | TA = 25°C | 4 | ||
| Package Thermal Resistance Junction-to-Ambient SOP-8 (Exposed Pad) | θJA | 49 | °C/W | Note 2: JEDEC 51-7 four-layer board, TA = 25°C, 70mm2 copper area | 4 | ||
| Package Thermal Resistance Junction-to-Case SOP-8 (Exposed Pad) | θJC | 8 | °C/W | Measured at exposed pad | 4 | ||
| Package Thermal Resistance Junction-to-Ambient SOP-8 (Exposed Pad), standard pad | θJA | 75 | °C/W | Standard SOP-8 (Exposed Pad) pad, 2.3 x 2.3 mm copper, JEDEC 51-7 four-layer board | 12 | ||
| Lead Temperature (Soldering) | 260 | °C | 10 sec soldering | 4 | |||
| Junction Temperature | TJ | 150 | °C | 4 | |||
| Storage Temperature Range | -65 | 150 | °C | 4 | |||
| ESD Susceptibility HBM | 2 | kV | HBM (Human Body Model) | 4 | |||
| Supply Input Voltage | VIN | 4.5 | 36 | V | 4 | ||
| Junction Temperature Range | TJ | -40 | 125 | °C | 4 | ||
| Ambient Temperature Range | TA | -40 | 85 | °C | 4 |
CAD (KiCad official)
- Symbol:
RT2862AGSP - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
rt2862agsp-etched.step/rt2862agsp-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt2862agsp.step/rt2862agsp.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (15 pp, sha256
c186bc5c8180a8a9, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).