RT2853BHGQW

{
  "slug": "rt2853bhgqw",
  "version": "0.1.0",
  "type": "component",
  "description": "Richtek Tech DC-DC Converters, QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "rt2853bhgqw",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
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    "README.md",
    "rt2853bhgqw.kicad_sym",
    "rt2853bhgqw.kicad_mod",
    "rt2853bhgqw.glb",
    "rt2853bhgqw.step",
    "rt2853bhgqw.lbr",
    "docs/hero.png",
    "docs/rt2853bhgqw-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "rt2853bhgqw-hero.glb",
    "rt2853bhgqw-hero.overlay.json",
    "rt2853bhgqw-etched.glb"
  ],
  "component": {
    "mpn": "RT2853BHGQW",
    "manufacturer": "Richtek Tech",
    "package": "QFN-16-EP(3x3)",
    "pin_count": 17,
    "category": "Power Management (PMIC)",
    "subcategory": "DC-DC Converters",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603026764826492928",
    "parts": {
      "symbol": "rt2853bhgqw.kicad_sym",
      "footprint": "rt2853bhgqw.kicad_mod",
      "model_3d": "rt2853bhgqw-hero.glb",
      "model_3d_plain": "rt2853bhgqw-etched.glb",
      "model_3d_step": "rt2853bhgqw-etched.step",
      "model_3d_step_plain": "rt2853bhgqw.step",
      "lbr": "rt2853bhgqw.lbr"
    },
    "distributor_links": {
      "lcsc": "C3034213"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T23:04:46Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "FB",
        "type": "input",
        "description": "Feedback input voltage: connect to the midpoint of the external feedback divider to sense VOUT, placed within 5mm of the FB pin, with the IC regulating VFB at 0.765V typical."
      },
      {
        "number": "2",
        "name": "VREG5",
        "type": "power_out",
        "description": "Internal regulator output, which needs a 1µF capacitor to GND to stabilize the output voltage."
      },
      {
        "number": "3",
        "name": "SS",
        "type": "passive",
        "description": "Soft-start control: an external capacitor between this pin and GND sets the soft-start time."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground pin."
      },
      {
        "number": "5",
        "name": "PGOOD",
        "type": "output",
        "description": "Open-drain power-good output that is pulled to PGND whenever VFB is less than 90% of its regulation threshold (typical)."
      },
      {
        "number": "6",
        "name": "EN",
        "type": "input",
        "description": "Enable control input: logic-high enables the converter, while logic-low forces shutdown and reduces supply current to less than 10µA; logic thresholds are 2V minimum high and 0.4V maximum low."
      },
      {
        "number": "7",
        "name": "PGND",
        "type": "power_in",
        "description": "Power ground connected to the source of the internal N-channel synchronous rectifier and to the other power-ground nodes; it should be well soldered to the input and output capacitors and a large PCB area."
      },
      {
        "number": "8",
        "name": "PGND",
        "type": "power_in",
        "description": "Power ground connected to the source of the internal N-channel synchronous rectifier and to the other power-ground nodes; it should be well soldered to the input and output capacitors and a large PCB area."
      },
      {
        "number": "9",
        "name": "SW",
        "type": "output",
        "description": "Switching node, the source of the internal high-side N-channel switch and drain of the synchronous rectifier; keep the trace to the inductor short and its area minimal to reduce EMI."
      },
      {
        "number": "10",
        "name": "SW",
        "type": "output",
        "description": "Switching node, the source of the internal high-side N-channel switch and drain of the synchronous rectifier; keep the trace to the inductor short and its area minimal to reduce EMI."
      },
      {
        "number": "11",
        "name": "SW",
        "type": "output",
        "description": "Switching node, the source of the internal high-side N-channel switch and drain of the synchronous rectifier; keep the trace to the inductor short and its area minimal to reduce EMI."
      },
      {
        "number": "12",
        "name": "BOOT",
        "type": "passive",
        "description": "Bootstrap supply for the high-side gate driver; connect a 0.1µF capacitor between BOOT and SW."
      },
      {
        "number": "13",
        "name": "VIN",
        "type": "power_in",
        "description": "Power input with an input voltage range of 4.5V to 18V; must be bypassed with a suitably large (10µF x 2) ceramic capacitor."
      },
      {
        "number": "14",
        "name": "VIN",
        "type": "power_in",
        "description": "Power input with an input voltage range of 4.5V to 18V; must be bypassed with a suitably large (10µF x 2) ceramic capacitor."
      },
      {
        "number": "15",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply input for the internal linear regulator that powers the IC; connect to the input voltage and bypass to ground with a 0.1µF ceramic capacitor."
      },
      {
        "number": "16",
        "name": "VS",
        "type": "power_in",
        "description": "Optional output-voltage discharge connection: an open-drain output that connects to ground when the device is disabled, and should be tied to VOUT if discharge is wanted."
      },
      {
        "number": "17",
        "name": "PGND",
        "type": "power_in",
        "description": "Exposed thermal pad, listed as PGND; it should be well soldered to the input and output capacitors and a large PCB area for good power dissipation."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin 4 is GND in the functional pin table, and pin 17 (exposed pad) is listed as PGND on page 9. The ; The page 2 top-view pin layout is garbled in the extracted text, so pin positions were not verified.; Pin 16 (VS) is described as an open-drain output that is optional and tied to ground when disabled. "
        ],
        "pages_sent": 8,
        "cost_usd": 0.0695,
        "at": "2026-10-18T23:02:31"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603026764826492928",
        "pages": 23,
        "sha256": "f0be9b8fcc2f1d5e",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 17,
        "described": 17,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
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        "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "rt2853bhgqw-etched.step",
        "role": "eda",
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        "sha256": "50963ed3d71cdba9a8b9a1be13e75cd3ad1ce2b597d559d921e938a7f1c2f076",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}